FPGA Parallel Data Transfer via PCIe Crossbar Switch
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Solution Overview
Problem
Current communication among field programmable gate arrays (FPGAs) requires significant host system involvement, which is undesirable for supercomputing applications, and lacks independent, direct, and parallel data transfer capabilities.
Innovation Solution
A system utilizing a PCIe communication network with a switch and non-blocking crossbar switches enables direct data transfers between FPGAs without host involvement, allowing for independent, direct, and parallel communication among multiple FPGAs, using DMA register messages to configure memory addresses and stream numbers for data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct FPGA-to-FPGA data transfers are implemented without host involvement, then communication speed and parallelism are improved, but system complexity increases due to the need for independent DMA configuration and communication protocols
Solution Approach 1:
The communication system is segmented into independent functional components: each FPGA has its own DMA engine and communication interface, allowing autonomous data transfers without host involvement. The PCIe switch is segmented into multiple independent communication channels, enabling parallel transfers between multiple FPGAs simultaneously.
Solution Approach 2:
Communication parameters including memory addresses, transfer sizes, and stream identifiers are pre-configured in DMA registers before data transfers begin. This preliminary configuration enables FPGAs to autonomously execute data transfers without real-time host intervention, improving speed while managing complexity through advance setup.
2Productivity
If multiple FPGAs communicate in parallel independently, then productivity is improved, but the difficulty of detecting and measuring communication states increases
Solution Approach 1:
The system incorporates feedback mechanisms through status registers and interrupt capabilities that allow FPGAs to report communication states and completion statuses. Stream identifiers track data flow states across parallel transfers, enabling monitoring and measurement of communication progress without simplifying the overall system complexity.
3Extent of automation
If host involvement is minimized for data transfers, then automation is improved, but configuration time increases due to the need for detailed DMA register setup
Solution Approach 1:
The DMA engine and communication interface are designed as universal, multi-functional components that can handle various data transfer scenarios (FPGA-to-FPGA, FPGA-to-PCIe, FPGA-to-memory) through a single unified architecture. This multi-functionality reduces configuration time by reusing the same hardware blocks and configuration procedures across different communication scenarios.
Data Source
AI summary
Representative embodiments are disclosed for data transfer between field programmable gate arrays (FPGAs). A representative system includes: a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines; a host computing system coupled to the PCIe communication network; a nonblocking crossbar switch; a plurality of memory circuits; and a plurality of field programmable gate arrays, each field programmable gate array configurable for a plurality of data transfers to and from the host computing system and any other field programmable gate array of the plurality of field programmable gate arrays, with each data transfer including a designation of a first memory address, a file size, and a stream number. Once base DMA registers have been initialized for a selected application, no further involvement by the host computing system is involved for the duration of the selected application.