External Phase Control for FPGA Clock Alignment Without Latency
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver and transmitter clock signals, which introduces unwanted latency and delays in processing, particularly in high-frequency applications like high-frequency trading, where precise timestamp accuracy is crucial.
Innovation Solution
A field programmable gate array system with an external phase controller that provides phase matching between receiver and transmitter clocks, using a deserializer and serializer to generate aligned clock signals and a phase control circuit to adjust the transmitter clock signal based on phase differences, eliminating the need for clock domain crossing circuits that introduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock domain crossing circuit is included in the FPGA to synchronize receiver and transmitter clock signals, then phase synchronization between clocks is improved, but processing delay increases
Solution Approach 1:
The patent extracts the phase synchronization function from the FPGA internal clock domain crossing circuit and relocates it to an external phase controller device. This separation allows the FPGA to process data without internal synchronization delays while the external device independently manages clock phase alignment, thus resolving the contradiction between achieving phase synchronization and minimizing processing delay.
2Reliability
If internal clock synchronization is implemented within the FPGA, then clock phase matching is achieved, but processing throughput decreases
Solution Approach 1:
The synchronization functionality is extracted from the FPGA fabric and implemented in an external phase controller. This allows the FPGA to operate at full throughput without internal synchronization overhead, while the external device ensures clock phase matching is maintained independently, thus resolving the trade-off between reliability and productivity.
3Reliability
If phase synchronization circuits are added to the FPGA, then clock alignment between receiver and transmitter is improved, but device complexity increases
Solution Approach 1:
The complex phase synchronization circuitry is extracted from the FPGA and implemented in a dedicated external phase controller device. This separates the clock management complexity from the data processing logic, allowing the FPGA to remain simple and focused on high-speed processing while the external device handles clock alignment, thus resolving the contradiction between reliability and device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables sub-microsecond processing throughput without introducing unnecessary delay, achieving phase alignment between receiver and transmitter clocks, thereby enhancing processing speed and accuracy in high-frequency applications.
Implementation Method 1
a phase detector operationally connected to the first clock output pin and the second clock output pin of the second interface of the field programmable gate array, and wherein the phase detector is configured to compare the third phase of the receiver side clock signal to the fifth phase of the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the third phase of the receiver side clock signal and the fifth phase of the transmitter side clock signal
Implementation Method 2
an adjustable oscillator operationally connected to the phase controller and configured to receive the adjustment information as well as operationally connected to the second reference clock pin of the first interface of the field programmable gate array, wherein the adjustable oscillator is configured to generate the second clock signal including the second frequency and the second phase based on the adjustment information
Data Source
AI summary
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.