FPGA Logic Placement and Routing Optimization
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Solution Overview
Problem
Conventional methods for implementing user logic in Field Programmable Gate Arrays (FPGAs) are limited in making gross corrections for optimal timing performance, especially in larger and more complex devices, where minor optimizations are insufficient to address significant timing violations.
Innovation Solution
A method and system that perform local optimization alongside global optimization during the placing and routing stages, using parameters like cell-type, cell-mapping, cell movement, cell packing density, and interconnect utilization density to make minor changes and improve timing performance, allowing for more effective placement and routing of user logic in FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If post placement optimization and post routing optimization are performed using conventional methods, then minor corrections can be made to placement and routing, but gross corrections cannot be performed and timing performance remains suboptimal in large FPGA devices
Solution Approach 1:
The implementation process is segmented into multiple passes including initial placement, initial routing, post placement optimization, and post routing optimization. Each pass focuses on specific optimization tasks, allowing gross corrections in early passes and fine-tuning in later passes, thereby addressing timing violations in large FPGA devices effectively
Solution Approach 2:
The method performs preliminary placement and routing actions before final optimization. The initial placement and routing passes establish a baseline configuration that can be progressively improved through subsequent optimization passes, enabling gross corrections to be made before fine-tuning
2Ease of manufacture
If conventional post placement and post routing optimization methods are used, then the processes can be completed with standard procedures, but they cannot address significant timing violations in larger FPGA devices
Solution Approach 1:
The optimization process is made dynamic through multiple iterative passes. The implementation tool automatically adjusts optimization strategies based on timing violation analysis from previous passes, transitioning from gross corrections to fine-tuning dynamically, thereby maintaining reliability in timing performance for large FPGA devices while managing process complexity
3Manufacturing precision
If multiple optimization passes are performed including post placement and post routing optimization, then timing performance can be improved, but the implementation process becomes more complex and time-consuming
Solution Approach 1:
The method applies partial optimization actions in each pass, focusing on specific timing violations rather than re-optimizing the entire design. Each pass addresses only the critical timing issues identified in timing analysis, avoiding unnecessary re-processing of well-performing regions, thereby reducing implementation time while maintaining timing performance
Data Source
AI summary
Embodiments of present disclosure relates to a method and a system for implementation of user logic in a FPGA device. For the implementation, user logic is mapped onto cells of the FPGA device in implementation platform associated with FPGA device. The mapping is based on user logic constraints to be met and received for FPGA device. Further, mapped cells of FPGA device are placed in implementation platform based on local mapping optimization parameters. The placing also comprises of performing placement optimization on placed cells of FPGA device. Upon placement, placed cells of FPGA device are routed in implementation platform based on at least local mapping optimization parameters and local placement optimization parameters. The routing also comprises of performing routing optimization on routed cells of FPGA device.