FPGA Internal PLL Phase Control for Low-Latency Clock Alignment

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Solution Overview

Problem

Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver and transmitter clock signals, leading to unwanted latency and processing delays, particularly in high-frequency applications like high-frequency trading where microsecond accuracy is crucial.

Innovation Solution

A field programmable gate array system with an internal phase controller that includes a phase detector and phase controller to align the receiver and transmitter clock signals, eliminating the need for clock domain crossing circuits and minimizing latency by adjusting the phase of the transmitter side clock to match the receiver side clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If clock domain crossing circuits are used to synchronize receiver and transmitter clocks in FPGA, then phase synchronization is achieved, but processing delay increases

Engineering Contradiction:

Improvephase synchronizationVSAvoidprocessing delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the phase alignment function from traditional clock domain crossing circuits and implements it separately using phase detectors and adjustable delay elements. This allows phase synchronization to be achieved independently, enabling the removal of unnecessary clock domain crossing circuits that introduce processing delays, thereby resolving the contradiction between achieving phase synchronization and minimizing processing delay.

Inventive Principle:

Principle #2Taking out (Extraction)

2Measurement precision

If traditional phase-locked loop with frequency measurement is used, then frequency synchronization is achieved, but phase synchronization accuracy is insufficient

Engineering Contradiction:

Improvephase measurement accuracyVSAvoidPLL configuration complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the measurement parameter from frequency to phase by implementing phase detectors that directly measure phase differences between receiver and transmitter clocks. This parameter change enables accurate phase synchronization without requiring complex PLL configurations, as the system can directly detect and compensate for phase offsets, resolving the contradiction between measurement precision and device complexity.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables sub-microsecond processing throughput without introducing unnecessary delays, achieving phase synchronization between receiver and transmitter clocks, thus enhancing processing efficiency and reducing latency in FPGA systems.

Implementation Method 1

a phase detector to compare the phase of the receiver side clock signal and the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the phase of the receiver side clock signal and the phase of the transmitter side clock signal

Methodology Applied

Scientific EffectPhase detection: