Post-Placement Routability Optimization in FPGA Design
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Solution Overview
Problem
Current methods for routability optimization in FPGA design often require inaccurate estimations of component placement, leading to ineffective optimizations, as they are typically performed before placement, resulting in inefficient wire length management.
Innovation Solution
The implementation of post-placement routability optimization techniques such as fanout splitting, logic duplication, and local rewiring within the EDA tools to reduce wire length by reconfiguring connections and duplicating logic elements after placement, ensuring more accurate resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If routability optimizations are performed before placement, then early wire length management is attempted, but the optimizations become ineffective due to inaccurate component position estimations
Solution Approach 1:
The patent performs routability optimization actions (fanout splitting, logic duplication, local rewiring) in advance during the placement stage, but uses actual placed component positions rather than estimations. This preliminary action with accurate position data enables effective wire length reduction before the routing stage begins.
Solution Approach 2:
Instead of performing routability optimization before placement as conventionally done, the patent inverts the sequence by performing it after placement but before routing. This reversal allows the use of actual component positions to guide optimization decisions, making the optimizations effective rather than speculative.
2Reliability
If multiple iterations are performed to satisfy placement and routing specifications, then routing quality improves, but design completion time increases significantly
Solution Approach 1:
The patent performs wire length reduction optimizations during the placement stage as a preliminary action before routing begins. By reducing wire lengths in advance using actual component positions, the subsequent routing stage requires fewer iterations to satisfy routing specifications, thereby reducing total design completion time while maintaining routing quality.
3Productivity
If wire length is reduced through post-placement optimizations, then routing efficiency improves, but design complexity increases due to additional optimization steps
Solution Approach 1:
The patent segments the routability optimization process into three distinct techniques: fanout splitting, logic duplication, and local rewiring. Each technique can be applied independently or in combination, allowing selective use based on design requirements. This segmentation manages complexity by providing modular, targeted optimization approaches rather than a monolithic complex process.
Solution Approach 2:
The EDA tool automatically performs the post-placement routability optimizations without requiring manual intervention. The tool self-manages the complex optimization process by automatically identifying candidates for fanout splitting, logic duplication, and local rewiring, and executing these transformations to reduce wire lengths, thereby improving routing efficiency while hiding the complexity from the user.
Data Source
AI summary
A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after placing the system. The system is routed after optimizing placement.