FPGA Power Estimation via Embedded Analysis Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current simulator-based system-on-chip (SoC) power estimation tools are inefficient for large systems due to low running speed, while hardware emulators are costly and not economically viable for widespread use.
Innovation Solution
A Field Programmable Gate Array (FPGA)-based system power estimation apparatus and method that incorporates a power analysis circuit to estimate power by retrieving and converting internal operation-state signals of target IP circuits using a power model, improving efficiency and reducing costs compared to traditional simulators and emulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a simulator is used for system power estimation, then software simulation can be performed, but running efficiency drops significantly for large systems
Solution Approach 1:
The patent replaces the software-based simulator with a hardware-based FPGA implementation. The power estimation function is transformed from a software simulation process to a hardware circuit operation, where the FPGA configures the target circuit and embedded power analysis circuits to directly measure and calculate power consumption in real-time, achieving millions of cycles per second efficiency
Solution Approach 2:
The patent introduces power analysis circuits as intermediary components embedded within the FPGA fabric. These circuits intercept and analyze internal operation-state signals from the target IP circuit, serving as a mediator between the target circuit and the power estimation function, enabling accurate power measurement without requiring external simulation
2Productivity
If an emulator is used for system power estimation, then hardware acceleration achieves high running efficiency, but the price is considerably high
Solution Approach 1:
The patent segments the power analysis function into separate, modular power analysis circuits that are distributed and embedded within the FPGA fabric. Each power analysis circuit handles specific IP blocks or circuit segments, allowing the power estimation functionality to be implemented using standard FPGA resources rather than requiring a complete expensive emulator system
Solution Approach 2:
The patent creates a universal power estimation platform using FPGA that can evaluate multiple different target IP circuits and system configurations. The same FPGA-based infrastructure with embedded power analysis circuits can be reconfigured to analyze different designs, replacing the need for multiple specialized emulator systems
Data Source
AI summary
A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.