FPGA Partial Reconfigurable Areas for Network Function Acceleration

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Solution Overview

Problem

Current network functions virtualization (NFV) systems in multi-core X86 systems experience high CPU overhead and low communication performance due to frequent access to physical machine CPUs during service processing, which hampers overall system efficiency.

Innovation Solution

A service deployment method and network functions acceleration platform utilizing a field-programmable gate array (FPGA) with partial reconfigurable areas, a configuration module, and a data flow forwarding module, connected via a PCIe data channel, where the FPGA loads an FPGA framework file to allocate hardware resources and configure PR areas for service processing, reducing CPU consumption by forwarding network packets to designated PR areas based on a forwarding flow table.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If service processing is performed by VM on physical machine CPU, then service deployment flexibility is improved, but CPU overhead increases and communication performance decreases

Engineering Contradiction:
Improveservice deployment flexibilityVSAvoidcommunication performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the service processing function into two parts: control plane functions remain on the VM for flexibility, while data plane functions are offloaded to dedicated PR areas on the FPGA for high-speed processing. This segmentation resolves the contradiction by separating flexible software control from performance-critical hardware acceleration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a network function acceleration platform as an intermediary between the VM and physical network interface. This platform includes PR areas on FPGA that act as mediators to handle packet forwarding and processing, reducing the burden on the physical machine CPU while maintaining VM-based service deployment flexibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If VM frequently accesses physical machine CPU for service processing, then service control flexibility is improved, but system overhead increases

Engineering Contradiction:
Improveservice control flexibilityVSAvoidCPU overhead
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The patent extracts the intensive packet processing functions from the VM-CPU interaction path and places them in dedicated PR areas on the FPGA. This extraction eliminates the need for frequent CPU accesses during packet forwarding, reducing CPU overhead while preserving VM control flexibility for service management.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The PR areas on the FPGA are configured to autonomously handle packet forwarding and processing tasks without requiring continuous CPU intervention. The hardware acceleration platform performs self-service for data plane operations, reducing the service control overhead on the physical machine while maintaining flexibility through VM configuration.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If general-purpose X86 system with VM is used for VNF deployment, then system versatility is improved, but processing speed decreases

Engineering Contradiction:
Improvesystem versatilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent applies local quality by creating specialized PR areas on the FPGA with hardware optimized for specific network function processing tasks. Each PR area is configured with dedicated resources and logic tailored to its specific function, providing high-speed processing for that particular service while the overall system maintains versatility through multiple configurable PR areas.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3684012B1Service deployment method and network function accelerating platform
Publication Date: 2023.06.21 HUAWEI TECH CO LTD
  • EP3684012B1 patent drawingFigure 1a
  • EP3684012B1 patent drawingFigure 1b
  • EP3684012B1 patent drawingFigure 2a

AI summary

Embodiments of the present invention disclose a service deployment method and a network functions acceleration platform, which are used for improving service processing speed and performance of a system. The method provided by the embodiments of the present invention includes: when the FPGA is powered on, loading, by the FPGA, an FPGA framework file, so that the FPGA includes M partial reconfigurable PR areas, a configuration module, and a data flow forwarding module; when receiving a service configuration instruction, generating, by the physical machine, a virtual machine VM, and selecting at least one PR area from the M PR areas to establish a correspondence with the VM; performing, by the configuration module, service resource configuration on the selected PR area according to a PR configuration resource, so that the selected PR area has a service processing capability; adding, by the configuration module, a forwarding entry corresponding to the PR area in the forwarding flow table, so that the data flow forwarding module forwards a received network packet to the corresponding PR area by searching the forwarding flow table.