FPGA Numerical Precision Switching for Machine Learning Compute
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Solution Overview
Problem
Conventional computing systems face challenges in efficiently supporting varying numerical precisions, as implementing different precision levels in hardware is costly and impractical, especially for niche applications, due to the need for extending instruction sets and high cycle times.
Innovation Solution
Field-programmable gate array (FPGA) devices are reconfigured to dynamically adjust numerical precision in real-time, allowing for a wide range of precision levels to be supported, optimizing computations by reducing unnecessary precision and improving energy use, memory access, and computational cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If different precision levels are implemented in hardware, then computation accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements dynamic precision adjustment by allowing the computational unit to change its numerical precision (e.g., between 16-bit and 32-bit floating point) during runtime based on the specific computation being performed. This is achieved through control logic that receives precision indicators and reconfigures the computational unit accordingly, eliminating the need for multiple fixed-precision hardware implementations.
Solution Approach 2:
The patent changes the precision parameter of the computational unit dynamically. By modifying the precision setting (e.g., switching between different floating-point formats) based on computation requirements, the system achieves high accuracy when needed while reducing hardware resource usage when lower precision suffices, thereby avoiding the complexity of implementing all precision levels simultaneously in hardware.
2Adaptability or versatility
If extended instruction sets are implemented to support varying precision, then adaptability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent creates a universal computational unit that can perform computations at multiple precision levels (e.g., 16-bit, 24-bit, 32-bit floating point) using the same hardware structure. The unit is controlled by precision indicators that specify which precision level to use for each computation, allowing a single manufactured device to adapt to various precision requirements without requiring different hardware versions.
3Measurement precision
If high precision is used for all computations, then computation accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent dynamically changes the precision parameter based on computation requirements. When high accuracy is needed, the system uses higher precision (e.g., 32-bit floating point); when lower precision suffices, it uses lower precision (e.g., 16-bit floating point). This adaptive approach reduces energy consumption by avoiding unnecessary high-precision computations while maintaining accuracy when required.
Data Source
AI summary
A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.