On-Chip Probe Circuit for FPGA Fault Detection
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Solution Overview
Problem
Current methods for testing FPGAs for delay defects are inefficient, particularly for programmable integrated circuits, as they require high design-dependent clock frequencies and lack effective means for controlling and observing flip-flops, making it difficult to test pre-programmed designs without reprogramming and consuming valuable logic capacity.
Innovation Solution
A read/write probe circuit with asynchronous load capability provides random access to flip-flops in the programmable fabric, enabling real-time observation and control, similar to a scan chain, allowing for efficient testing of delay defects without additional logic overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chain circuitry is added to FPGAs to provide controllability and observability of flip-flops, then fault coverage is improved, but area overhead increases
Solution Approach 1:
The probe circuit is designed to serve multiple functions: it provides both controllability (writing test patterns to flip-flops) and observability (reading flip-flop outputs), and can be used for both delay defect testing and functional debugging. This multi-functionality eliminates the need for separate dedicated test circuits, reducing area overhead while maintaining comprehensive fault coverage.
Solution Approach 2:
The invention introduces an intermediary probe circuit that mediates between the external tester and the FPGA's internal flip-flops. This probe circuit includes address decoding logic that translates external address inputs into selective control signals for specific flip-flops, enabling random access without requiring a full scan chain infrastructure. The intermediary nature of this circuit allows efficient area utilization while providing complete controllability and observability.
2Reliability
If multiple test designs are programmed into the FPGA to achieve comprehensive defect coverage, then testing effectiveness is improved, but productivity decreases due to reprogramming requirements
Solution Approach 1:
The probe circuit is built into the FPGA's fabric during manufacturing, before any testing or programming occurs. This preliminary integration means that the circuit is already in place and functional when the FPGA receives its first programming, eliminating the need to reprogram multiple test designs. The pre-configured probe circuit enables immediate access to flip-flops for testing purposes.
Solution Approach 2:
The probe circuit enables the FPGA to perform its own self-testing and self-diagnosis capabilities. By providing direct access to internal flip-flops, the circuit allows the device to monitor its own operational state, detect delay defects, and provide debugging information without requiring external reprogramming or multiple test configurations. This self-service capability significantly improves productivity.
3Area of stationary object
If a read-only probe circuit is used to observe flip-flop outputs, then area overhead is reduced, but controllability is lost
Solution Approach 1:
The invention merges the read and write functions into a single integrated probe circuit. The same physical circuit infrastructure is used for both observing flip-flop outputs and loading test patterns into flip-flops. This is achieved by using multiplexers that can switch between input sources based on the desired operation mode, combining what would traditionally be separate read-only and write-capable circuits into one unified structure, thereby maintaining low area overhead while achieving full controllability.
Data Source
AI summary
An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.