FPGA-Based Protection Group Switching for Optical Networks
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Solution Overview
Problem
Existing optical transport networks (OTN) face challenges in rapid and efficient protection switching, particularly in multi-group scenarios, where batch switching operations lead to prolonged traffic recovery times due to serial processing, making it difficult to meet the requirement of less than 50 milliseconds for network availability.
Innovation Solution
A hardware-based protection group switching method utilizing a Field Programmable Gate Array (FPGA) to transmit switching triggering information to protection state machines via a hardware bus, allowing parallel operation of APS protocols, updating cross connection tables, and configuring them to cross connection or packet switching chips, thereby enabling efficient multi-group protection switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If serial processing is used for batch switching operations, then device complexity is reduced, but traffic recovery time increases beyond 50 milliseconds
Solution Approach 1:
The protection switching system is segmented into multiple independent protection state machines (PSM), each handling a specific protection group. This segmentation enables parallel processing of multiple protection groups simultaneously, reducing the overall traffic recovery time from serial processing to within the 50ms requirement while distributing the processing complexity across multiple specialized units.
Solution Approach 2:
The system transitions from one-dimensional serial processing to multi-dimensional parallel processing by implementing multiple protection state machines that operate concurrently. Each PSM processes its assigned protection group independently in parallel, effectively adding a temporal dimension to the processing architecture and achieving sub-50ms recovery times without proportionally increasing overall system complexity.
2Speed
If parallel processing of APS protocols is implemented, then switching speed increases, but hardware complexity increases due to FPGA requirements
Solution Approach 1:
The system replaces traditional software-based or general-purpose hardware APS protocol processing with dedicated hardware state machines implemented in FPGA. This substitution of processing mechanics enables true parallel execution of multiple APS protocols simultaneously, achieving high switching speeds while the FPGA's reconfigurable nature keeps hardware complexity manageable through standardized modular PSM designs.
Solution Approach 2:
The FPGA-based protection state machines are designed with universal functionality to handle multiple protection group configurations through parameterization. Each PSM can be configured to manage different protection groups with varying traffic flows and switching requirements, allowing the same hardware architecture to serve multiple functions and reduce overall hardware complexity despite parallel processing demands.
3Productivity
If multiple protection state machines are implemented in FPGA, then multi-group protection switching performance improves, but manufacturing complexity increases
Solution Approach 1:
The protection switching functionality is segmented into discrete, independently manufacturable protection state machine modules within the FPGA. Each PSM represents a self-contained functional unit that can be designed, tested, and manufactured independently, then integrated into the overall system. This modular segmentation improves protection switching performance while simplifying the manufacturing process through standardized module replication.
Solution Approach 2:
The protection state machines are designed with configurable parameters that allow the same hardware template to be adapted for different protection group scenarios. By changing parameters rather than designing separate hardware for each protection group, the system achieves high multi-group protection switching performance while reducing manufacturing complexity through parameterized design reuse across multiple instances.
Data Source
AI summary
Disclosed is a hardware-based protection group switching method and optical communication equipment. The method includes: transmitting, by a FPGA in equipment when detecting switching triggering information indicating that a local network element possibly has switching triggering situations, the switching triggering information to each protection state machine through a hardware bus; determining, by each protection state machine according to related traffic flow information, one or more related protection groups that are possibly affected by each switching triggering situation, and generating each corresponding switching triggering condition according to each piece of switching triggering information; separately querying, by the protection state machines corresponding to the related protection groups, a pre-stored table for APS protocol operation results; and updating a cross connection table according to the operation results, and configuring the updated cross connection table to a cross connection chip or a packet switching chip through the FPGA.