FPGA Protocol Engine for Multi-Protocol ATE Testing

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Solution Overview

Problem

Conventional automated test equipment (ATE) systems are limited in the number of devices under test (DUTs) they can handle simultaneously due to processing load on the tester processor and bandwidth constraints, and require protocol-specific hardware bus adapter cards, making it inefficient to test DUTs with different communication protocols.

Innovation Solution

The solution involves transferring command and test pattern generation functionality to Field-Programmable Gate Array (FPGA) devices, allowing for reconfigurable protocol engines on FPGAs, which reduces processing load on the tester processor and eliminates the need for protocol-specific hardware bus adapter cards, enabling simultaneous testing of multiple DUTs with different protocols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional ATE systems use protocol-specific hardware bus adapter cards, then each protocol can be tested with dedicated hardware, but the system complexity increases and requires hardware changes to test different protocols

Engineering Contradiction:

Improveprotocol testing capabilityVSAvoidhardware configuration

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The FPGA-based protocol engine is designed to perform multiple protocol testing functions within a single hardware platform. The engine can be dynamically reconfigured to support different communication protocols (PCIe, USB, SATA, SAS, etc.) without requiring physical hardware changes, thereby achieving universal protocol testing capability while reducing overall system complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The protocol engine implements dynamic reconfiguration capability through FPGA technology, allowing the hardware logic to be programmatically changed during operation or between test cycles. This dynamic adaptability enables the same physical hardware to seamlessly switch between different protocols, eliminating the need for static protocol-specific adapter cards

Inventive Principle:

Principle #15Dynamics

2Productivity

If the tester processor generates all commands and test patterns, then protocol-specific processing can be implemented, but the processing load limits the number of DUTs that can be tested simultaneously

Engineering Contradiction:

Improvenumber of DUTs tested simultaneouslyVSAvoidtester processor load

Core Design Contradiction:

ProductivityVSPower

Solution Approach 1:

The testing system is segmented into distinct functional components: the tester processor handles high-level test orchestration and control, while the FPGA-based protocol engine handles protocol-specific command generation, data pattern creation, and device communication. This segmentation distributes the processing load, enabling the system to test more DUTs simultaneously without overwhelming the tester processor

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The FPGA-based protocol engine acts as an intermediary between the tester processor and the devices under test. It receives minimal control signals from the tester processor and autonomously generates the complex protocol-specific commands and test patterns, thereby reducing the processing burden on the tester processor while maintaining protocol accuracy

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If the system uses hardware bus adapter cards for each protocol, then protocol-specific testing is supported, but bandwidth constraints limit the number of simultaneous DUTs

Engineering Contradiction:

Improvetesting throughputVSAvoidbandwidth resources

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The FPGA-based protocol engine provides universal interface functionality that can adapt to multiple protocols through software reconfiguration rather than requiring separate physical adapter cards for each protocol. This consolidates bandwidth resources into a single high-capacity interface while maintaining the ability to test multiple protocols simultaneously at high throughput

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10161993B2Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block

Publication Date: 2018.12.25 ADVANTEST CORP

AI summary

Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs. Each of the plurality of hardware accelerator circuits comprises a pattern generator circuit configurable to automatically generate test pattern data and a comparator circuit configured to compare data.