FPGA-Based Prototype Verification for Fault-Tolerant Computer Interconnection
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Solution Overview
Problem
High-end fault-tolerant computer systems face challenges in verifying the interconnection of multiple processors and large-scale integrated circuit designs due to increasing complexity and verification costs.
Innovation Solution
A prototype verification system comprising interconnected single junction prototype verification systems and an interconnection router chipset, utilizing four-path tightly-coupled computer boards with FPGA chips for protocol interconnection and cache consistency control, to enhance system interconnection and reduce verification costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors is increased to improve system performance, then system performance is improved, but device complexity increases
Solution Approach 1:
The verification system is divided into multiple single junction prototype verification systems, each handling a subset of processors. This segmentation allows the complex multi-processor verification to be broken down into manageable modular units that can be verified independently and then integrated.
Solution Approach 2:
An interconnection router chipset is introduced as an intermediary component to manage the complex interconnections between multiple processors and junction controllers. This intermediary abstracts the complexity of direct processor-to-processor communication through standardized interconnection protocols.
2Productivity
If bulky multi-channel computer system is constructed to meet application demand, then system performance is improved, but verification cost increases
Solution Approach 1:
The verification system uses multiple identical single junction prototype verification systems that can be replicated and configured in different quantities based on verification needs. This modular approach allows verification costs to be scaled appropriately rather than requiring a complete custom verification system for each configuration.
Solution Approach 2:
The invention uses field-programmable gate array (FPGA) chips to create reconfigurable copies of junction controller logic. These FPGA-based prototypes can be programmed to simulate different junction controller behaviors and configurations, reducing the need for multiple physical custom verification systems.
3Adaptability or versatility
If junction controller chipset and interconnection router chipset are used to finish system interconnection, then system interconnection capability is improved, but device complexity increases
Solution Approach 1:
The interconnection router chipset is designed with universal interconnection protocols that can handle multiple types of communication patterns and data formats. This multi-functional design allows a single chipset to support various interconnection scenarios without requiring separate specialized components for each protocol.
Solution Approach 2:
The junction controller acts as an intermediary between processors and the interconnection router chipset, translating processor-specific communication requirements into standardized router protocols. This intermediary layer simplifies the overall system complexity by providing a clear separation of concerns.
Data Source
AI summary
A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.