FPGA Key Storage Using PUF and BEOL Tamper-Resistant Memory

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing Field Programmable Gate Arrays (FPGAs) are vulnerable to security breaches due to discoverable encryption keys stored in static random access memory (SRAM) or embedded flash, allowing unauthorized access and modification of bit files.

Innovation Solution

Implementing a tamper-resistant design by storing encryption keys in a physical unclonable function (PUF) and writing them to tamper-resistant memory associated with the back end of the line (BEOL) of the FPGA, along with look-up tables (LUTs) in the same memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If encryption keys are stored in SRAM or embedded flash, then the FPGA can operate with standard memory components, but the encryption keys become discoverable through side channel attacks or PICA

Engineering Contradiction:
ImprovesecurityVSAvoidvulnerability to attacks
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the encryption key storage function from conventional memory components (SRAM, embedded flash) and relocates it to tamper-resistant memory associated with the back end of the line (BEOL). This separation removes the vulnerability to traditional attack vectors while maintaining the essential encryption key storage function.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces tamper-resistant memory as an intermediary component between the encryption keys and potential attackers. This intermediary layer provides physical and logical protection, preventing direct access to the keys while allowing authorized operations to proceed normally.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If encryption keys are stored in tamper-resistant memory in the BEOL, then security is enhanced, but the device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoidmemory architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the encryption key storage function with the BEOL memory structure, combining security functionality with existing architectural layers. This integration approach reduces overall system complexity by utilizing available infrastructure rather than adding completely separate components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The tamper-resistant memory in the BEOL serves multiple functions: it provides secure key storage, maintains compatibility with existing FPGA operations, and potentially supports other security-related operations. This multi-functionality reduces the need for dedicated separate components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If encryption keys are stored in conventional memory, then the FPGA has simpler architecture, but external memory and energy are required for secure operation

Engineering Contradiction:
Improvememory architectureVSAvoidenergy consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The tamper-resistant memory in the BEOL provides self-securing capabilities, automatically protecting encryption keys without requiring external security hardware or additional energy-consuming security subsystems. The memory structure itself provides the security function, eliminating the need for external protective measures.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4315141B1Trusted field programmable gate array
Publication Date: 2026.03.04 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • EP4315141B1 patent drawingFigure 1
  • EP4315141B1 patent drawingFigure 2
  • EP4315141B1 patent drawingFigure 3~4

AI summary

An approach to creating a tamper-resistant field programmable gate array (FPGA) and remotely reprogramming the tamper-resistant FPGA. In one aspect, determining if an encryption key is stored in a physical unclonable function (PUF) of the FPGA. Further, responsive to the encryption key not being stored in a PUF, writing an encryption key in tamper resistant memory associated with a back end of the line (BEOL) of the FPGA. In another aspect, writing a program key and a look-up table (LUT) in the tamper resistant memory.