FPGA RAM Block Ganging with Hardwired Enable Decoding
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Solution Overview
Problem
In field programmable gate array (FPGA) architectures, combining RAM blocks to achieve higher capacity while minimizing power consumption and delay is challenging due to the need for additional logic and power consumption when enabling multiple blocks for every read operation.
Innovation Solution
Implementing a composite RAM block with hardwired decoding logic and programmable enable inputs, allowing each block to be enabled only when uniquely selected for a read operation, and using an OR gate instead of a multiplexer to reduce delay and power consumption by forcing outputs to a known state when disabled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple RAM blocks are enabled for every read operation to achieve higher capacity, then the RAM capacity is increased, but the dynamic power consumption increases proportionally
Solution Approach 1:
The patent implements dynamic enabling of RAM blocks by introducing programmable enable inputs that allow each block to be selectively activated only when needed. The enable logic dynamically determines which blocks are active based on read operations, preventing unnecessary power consumption in inactive blocks while maintaining high capacity when multiple blocks are ganged together.
2Use of energy by moving object
If soft gates are used to decode address bits and control enable signals for each RAM block, then power consumption is reduced by enabling only selected blocks, but additional delay is incurred in the speed path
Solution Approach 1:
The patent replaces soft gate logic with hardwired decoding logic implemented as dedicated logic elements within the RAM block structure. This substitution eliminates the delay associated with soft gate decoding while maintaining the power-saving benefit of selective block enabling, as the hardwired logic provides a direct, low-latency path for enable signal generation.
Solution Approach 2:
The patent introduces dedicated logic elements as intermediaries between the address inputs and the RAM block enable signals. These logic elements perform the decoding function with minimal delay, acting as efficient mediators that translate address bits into block enable signals without the overhead of soft gate operations.
3Ease of operation
If a multiplexer is used to select the output of one enabled RAM block, then the correct data is routed to the output, but additional delay is incurred due to the multiplexer in the speed path
Solution Approach 1:
The patent extracts the output selection function from the critical read path by using separate enable signals for each RAM block instead of a multiplexer. Each block's output is independently enabled or disabled based on the read operation, removing the multiplexer delay from the speed path while maintaining the ability to select which block's output appears at the final output.
4Use of energy by moving object
If additional logic such as AND gates and multiplexers is added to gang RAM blocks efficiently, then power consumption is reduced and capacity is increased, but device complexity increases
Solution Approach 1:
The patent merges the enable logic and decoding functionality directly into the RAM block structure as integrated logic elements. By combining these functions within the block itself rather than adding separate external components, the patent reduces overall device complexity while maintaining the power-saving benefits of selective enabling and the capacity benefits of ganging multiple blocks.
Data Source
AI summary
A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.