FPGA True Random Number Generator With Self-Configured Delay Matching
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Solution Overview
Problem
Implementing True Random Number Generators (TRNGs) on reconfigurable hardware devices like FPGAs is challenging due to limited resources and design constraints, such as portability and reproducibility issues across different FPGA families and vendors, especially with timing jitter-based designs which require precise control over timing delay variations.
Innovation Solution
A true random number generator design that uses two digital devices with configurable delay lines, a sampling unit, and a controller circuit to monitor and adjust the delay difference between signals, allowing for automatic configuration and matching of the devices to achieve a 'good' matching, thereby reducing design effort and ensuring portability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing jitter based TRNG designs are used on FPGAs, then entropy generation is achieved, but precise control over timing delay variations is required which increases design complexity
Solution Approach 1:
The system performs self-testing and self-configuration through the controller circuit that automatically monitors delay differences and adjusts multiplexer configurations without external intervention, reducing design complexity while maintaining reliable entropy generation
Solution Approach 2:
The controller circuit continuously monitors the delay difference between signals and provides feedback to adjust multiplexer configurations, automatically maintaining optimal timing conditions for entropy generation without requiring precise manual control
2Reliability
If manual placement and routing constraints are applied to achieve good matching, then entropy quality is improved, but portability across different FPGA families is reduced
Solution Approach 1:
The system dynamically configures multiplexer connections based on measured delay characteristics, adapting to different FPGA families and process variations automatically, thereby maintaining entropy quality across diverse hardware platforms without fixed placement constraints
Solution Approach 2:
The controller circuit changes operational parameters (multiplexer configuration) based on measured delay differences, allowing the system to adapt to different FPGA families and process variations while maintaining consistent entropy quality
3Reliability
If search procedure is performed for each individual device to find suitable placement, then reproducibility is improved, but design effort and time are significantly increased
Solution Approach 1:
The system performs automatic self-configuration through controller-driven multiplexer adjustment based on measured delay characteristics, eliminating the need for manual search procedures while ensuring reproducible entropy generation across devices
Solution Approach 2:
The system performs preliminary measurement of delay characteristics and automatically configures multiplexers before entropy generation begins, ensuring reproducible results without requiring time-consuming manual search procedures
4Productivity
If two ring oscillators are used as entropy source, then throughput of 1 Mbit/s is achieved, but matching periods is challenging requiring repeated search procedure for every device
Solution Approach 1:
The controller circuit measures delay differences between the two ring oscillators and provides feedback to adjust multiplexer configurations, automatically achieving period matching and maintaining 1 Mbit/s throughput without repeated search procedures
Solution Approach 2:
The system dynamically adjusts multiplexer connections based on real-time delay measurements, enabling automatic period matching of the two ring oscillators while maintaining high throughput across different devices
Data Source
AI summary
A random number generator includes an entropy source comprising a first digital device arranged to apply to an input signal a first delay value to obtain a first signal and a second digital device arranged to apply to the input signal a second delay value different from the first delay value to obtain a second signal; a sampling unit configured to sample one of the first and second signals using the other signal as reference clock, thereby obtaining a sampled signal; measurement means to perform measurements of the sampled signal's delay difference with respect to the reference clock; a controller circuit arranged to monitor the measured delay difference of the sampled signal and to check the values of the measured delay difference and, once a given condition related to the values is met, to output a configuration signal.