FPGA Readback Signal Identification via Automatic Model Analysis
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Solution Overview
Problem
The existing process of FPGA-based real-time simulations is hindered by long development cycles due to the inability to access and modify model signals during operation, as signals become readable only at the end of the build process, requiring explicit modeling and retranslation, which is time-intensive.
Innovation Solution
A method for automatically identifying and outputting model signals readable via readback before completing the FPGA code generation, allowing for early adaptation of the FPGA model to ensure signal readability, using automatic analysis during the generation process, including detection of registers and time-delay elements, and recursive analysis of hierarchical models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If explicit modeling and retranslation are performed to make signals readable from FPGA, then signal readability is improved, but development time increases significantly
Solution Approach 1:
The patent performs automatic analysis of the FPGA model during the code generation process to identify signals that can be read back, before the FPGA build is completed. This preliminary identification allows developers to know which signals are readable in advance, eliminating the need for time-consuming explicit modeling and retranslation cycles that were previously required to ensure signal readability.
2Difficulty of detecting and measuring
If signal tracing is performed manually in large models, then signal identification is possible, but complexity and time consumption increase
Solution Approach 1:
The patent implements an automatic analysis mechanism that performs signal tracing and identification autonomously during the FPGA code generation process. The system analyzes the FPGA model, traces signal paths, and identifies readable signals without requiring manual intervention, thereby reducing both the complexity burden and time consumption associated with manual signal tracing in large models.
3Reliability
If FPGA code generation is completed fully before readback analysis, then code completeness is ensured, but development cycle lengthens
Solution Approach 1:
The patent performs readback analysis during the FPGA code generation process itself, rather than waiting for complete code generation to finish. This preliminary analysis identifies readable signals early in the build process, allowing developers to adapt the FPGA model accordingly before code generation completes, thereby shortening the overall development cycle while maintaining code completeness through iterative refinement.
Data Source
AI summary
A method for automatically determining models signals of an FPGA program which are readable from the FPGA with the aid of a readback following an FPGA build, including the following steps: generating an FPGA model and generating an FPGA code from the FPGA model, the method comprising the additional step of an automatic analysis for the purpose of identifying signals which are readable from the FPGA with the aid of a readback, prior to the completion of the step of generating the FPGA code from the FPGA model, and the method comprises the step of outputting signals which are readable from the FPGA with the aid of a readback. A data processing device is also provided for carrying out the method.