FPGA Relay Logic Reflash Detection and Propagation
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Solution Overview
Problem
Current performance monitoring systems using Field Programmable Gate Arrays (FPGAs) face challenges in efficiently detecting and propagating relay reflash events within Boolean relay logic, requiring external hardware for processing and detection.
Innovation Solution
Integration of a relay logic evaluator and controller within the FPGA to detect and propagate reflash events by counting status changes and generating a signal indicative of the count, which can be visually represented through a flashing light, eliminating the need for external hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If external hardware is used for processing and detection of reflash events, then detection capability is provided, but device complexity and hardware requirements increase
Solution Approach 1:
The patent merges the reflash detection functionality with the existing FPGA relay logic evaluator and controller. The controller internally counts status changes using its existing processing capabilities and generates reflash signals without requiring separate external detection hardware. This integration eliminates the need for additional external components while maintaining full detection capability.
2Device complexity
If reflash detection is integrated within the FPGA, then device complexity is reduced, but processing capability may be limited
Solution Approach 1:
The controller within the FPGA is designed to perform multiple functions: it evaluates relay logic, counts status changes, detects reflash events, and generates output signals. By making the controller multi-functional, the system achieves integrated reflash detection without sacrificing processing capability, as the same hardware resources are utilized for multiple purposes.
Solution Approach 2:
The FPGA controller serves itself by using its internal resources to detect and process reflash events. The controller monitors its own input signals, counts status changes, and generates reflash output signals without requiring external assistance. This self-service approach reduces hardware complexity while maintaining processing efficiency.
3Loss of information
If multiple status changes are counted and visualized, then information completeness is improved, but output signal complexity increases
Solution Approach 1:
The patent uses a visual indicator (such as an LED) that changes its flash pattern to represent different counts of status changes. Instead of using complex multi-bit output signals, the system translates the count information into a human-readable visual display where the number of flashes corresponds to the number of status changes detected, simplifying the output interface while preserving information.
Data Source
AI summary
A relay logic evaluator includes circuitry configured to receive signals indicative of a status change. The circuitry is configured to send a second signal indicative of the status changes received by the circuitry. A controller is coupled to the relay logic evaluator. The controller is configured to determine a value indicative of a count of status changes responsive to receiving the second signal from the circuitry. The controller is configured to provide a signal indicative of the value.