FPGA Cluster Low-Latency Relinearization for Homomorphic Encryption
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Solution Overview
Problem
Homomorphic encryption processes are slow due to high computation overhead, and existing acceleration techniques do not adequately address latency issues.
Innovation Solution
A low-latency relinearization method implemented by a field programmable gate array (FPGA) cluster, which performs modular reduction, multiplication, and summation operations in a pipeline fashion, including transforming vectors between Number Theoretic Transform (NTT) and Inverse Number Theoretic Transform (INTT) domains, to generate intermediate and result vectors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If homomorphic encryption is implemented using standard computational methods, then security and privacy preservation are achieved, but computation speed becomes significantly slow due to high computation overhead
Solution Approach 1:
The patent replaces general-purpose software-based homomorphic encryption computation with specialized hardware circuitry designed specifically for HE operations. This hardware acceleration substitutes the mechanical/software execution model with an optimized hardware implementation, achieving speedups of 10-100x while maintaining the security properties of homomorphic encryption through faithful implementation of the cryptographic algorithms.
Solution Approach 2:
The patent optimizes computational parameters by transforming polynomials between different domains (NTT and INTT domains) to minimize computation overhead. By carefully selecting and changing computational parameters such as modulus values, transform domains, and evaluation points, the system achieves faster computation while preserving the mathematical correctness and security guarantees of homomorphic encryption operations.
2Productivity
If homomorphic encryption is accelerated using existing FPGA-based hardware, then computation speed is improved, but latency remains high due to sequential processing bottlenecks
Solution Approach 1:
The patent segments the homomorphic encryption computation into distinct functional stages including polynomial transformation, modular multiplication, and result combination. Each stage is implemented as an independent hardware module that can process data in parallel, eliminating sequential bottlenecks and reducing overall latency while maintaining the computational integrity required for secure homomorphic operations.
Solution Approach 2:
The patent performs preliminary transformations of polynomials into the number-theoretic transform domain before executing multiplication operations. This preliminary action pre-processes the data into a form that enables faster computation during the critical multiplication phase, thereby reducing the time required for the most computationally intensive operations in the homomorphic encryption pipeline.
3Ease of manufacture
If polynomial multiplication is performed in the time domain, then computational simplicity is maintained, but transformation to frequency domain adds processing overhead
Solution Approach 1:
The patent changes the computational parameter from time-domain evaluation to frequency-domain evaluation using the number-theoretic transform. Although this requires initial transformation overhead, it enables much faster multiplication operations in the frequency domain where polynomial multiplication reduces to simple element-wise multiplication, followed by an inverse transform to obtain the final result.
Data Source
AI summary
A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.