FPGA Resequencing Analysis for Parallel Alignment and Deduplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing resequencing analysis methods suffer from low execution efficiency and slow analysis rates due to serial execution of processes, particularly in aligning, sorting, and deduplicating genome sequencing data.
Innovation Solution
Implementing an FPGA-based resequencing analysis method that parallelizes the processes of aligning, sorting, and deduplicating genome sequencing data using separate threads on an FPGA and CPU, with correction based on base quality values, to enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial execution of aligning, sorting, and deduplicating processes is used, then device complexity is reduced, but productivity and execution efficiency deteriorate
Solution Approach 1:
The patent divides the resequencing analysis process into three independent functional modules: alignment (first task), sorting (second task), and deduplication (third task). Each module can be executed independently and in parallel, with the alignment module processing sequencing data to generate alignment results, the sorting module organizing these results, and the deduplication module removing duplicate entries. This segmentation enables concurrent execution across multiple processing units, significantly improving productivity while maintaining manageable complexity through clear module boundaries.
Solution Approach 2:
The patent transitions from serial one-dimensional execution to parallel multi-dimensional processing by implementing the three tasks simultaneously on different processing units (CPU threads, GPU cores, or FPGA logic units). This dimensional shift allows the system to process alignment, sorting, and deduplication operations in parallel time slices rather than sequentially, achieving substantial speedup in resequencing efficiency without proportionally increasing device complexity.
2Loss of time
If parallel processing is implemented for aligning, sorting, and deduplicating, then execution efficiency and analysis rate improve, but device complexity increases
Solution Approach 1:
By segmenting the processing workflow into distinct alignment, sorting, and deduplication tasks with well-defined interfaces and data flow, the patent enables parallel execution while controlling complexity. Each segmented module processes specific aspects of the data independently, reducing inter-module dependencies and synchronization overhead, thus minimizing the complexity increase associated with parallel implementation.
Solution Approach 2:
The patent employs universal processing units (CPU threads, GPU cores, or FPGA logic elements) that can perform multiple functions. The same type of processing unit handles alignment, sorting, and deduplication operations through different computational kernels or logic configurations, rather than requiring specialized hardware for each function. This multi-functionality reduces overall device complexity while achieving parallel processing benefits.
3Productivity
If multiple threads are allocated for parallel processing, then calculation cost and running time reduce, but resource allocation complexity increases
Solution Approach 1:
The patent segments the computational workload into three distinct task types (alignment, sorting, deduplication) that can be independently allocated to different threads or processing units. This segmentation simplifies resource allocation by allowing the system to assign entire functional modules to specific threads rather than managing fine-grained task distribution, reducing the complexity of thread management while maintaining high parallelism and analysis rate.
Data Source
Figure 1~2
Figure 3~4
Figure 5~7
AI summary
Proposed by the present disclosure are an FPGA-based resequencing analysis method and device, wherein the method comprises: receiving genomic resequencing data; using the resequencing data as an input of an FPGA, determining a comparison result in the resequencing process according to an output of the FPGA, and simultaneously performing sorting and deduplication processing on the comparison result; correcting a base quality value of the comparison result after sorting and deduplication processing; and detecting a mutation result according to the corrected comparison result. The described method may save program running time, save calculation costs, and improve resequencing efficiency.