FPGA Resource Allocation for Deterministic Data Processing
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Solution Overview
Problem
Enterprises face challenges in efficiently allocating processing resources for data sets due to the non-deterministic nature of microprocessor processing, leading to over-allocation of resources, inefficient use of processing capacity, and difficulty in detecting processing errors in a timely manner.
Innovation Solution
A system for allocating field-programmable gate array (FPGA) resources that determines the minimum number of FPGAs needed based on data set size, available time, and operational clock speed, categorizes data and FPGAs by processing requirements, and allocates them accordingly to ensure efficient processing and real-time error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microprocessors are allocated to process data sets, then data processing can be performed, but the non-deterministic nature of microprocessor processing makes it difficult to estimate processing time and ensures deadlines are met only by over-allocating resources
Solution Approach 1:
The patent replaces microprocessor-based software processing with FPGA hardware processing. FPGAs implement processing logic directly in hardware through configurable logic blocks and interconnects, providing deterministic processing times that can be precisely estimated and controlled, eliminating the need for over-allocation to ensure deadline compliance
Solution Approach 2:
The patent changes the fundamental processing parameter from software-execution-time (non-deterministic) to hardware-circuit-delay (deterministic). By configuring FPGAs with specific logic circuits, the processing time becomes a fixed physical parameter that can be precisely measured and guaranteed, allowing accurate resource allocation without over-provisioning
2Reliability
If timeout delays are used to detect processing errors, then error detection is possible, but the non-deterministic processing time requires unreasonably large timeout delays that are effectively ignored
Solution Approach 1:
The patent replaces software-based timeout error detection with hardware-based deterministic timing. FPGA circuits provide predictable execution paths with known maximum delays, allowing timeout values to be set based on actual processing requirements rather than arbitrary large numbers, making error detection practical and effective
Solution Approach 2:
The patent implements precise timing feedback mechanisms where the system monitors actual processing time against predetermined thresholds. Because FPGA processing times are deterministic and measurable, the feedback loop can accurately detect when processing exceeds expected durations, enabling reliable error detection with appropriately scaled timeout values
3Productivity
If processing resources are allocated without optimization, then all data can be queued for processing, but high processing capacity resources are wasted on low processing requirements while data with higher requirements remain queued
Solution Approach 1:
The patent applies local quality by matching specific FPGA resources to specific data processing requirements. Different FPGAs can be configured with different logic circuits optimized for different types of processing tasks, and the allocation system assigns data to FPGAs based on their specific capabilities and current workload, ensuring efficient utilization of heterogeneous processing resources
Solution Approach 2:
The patent implements dynamic resource allocation where the system continuously monitors processing requirements and availability, adjusting assignments in real-time. This dynamic approach allows the system to respond to changing workloads and optimize the matching between data requirements and FPGA capabilities, maximizing throughput while minimizing idle capacity
Data Source
AI summary
A system for allocating field programmable gate array (FPGA) resources, comprises a plurality of FPGAs operable to implement one or more pipeline circuits; and one or more processors operable to determine the size of a set of data to be processed, determine an amount of time available to process the data set, determine an operational clock speed for the plurality of FPGAs, determine, based at least in part on the determined size of the set of data, the determined amount of time, and the determined operational clock speed, a number of FPGAs to allocate to process the set of data within the determined amount of time, and allocate at least the determined number of the plurality of FPGAs to process the set of data.