FPGA Resource Allocation for Deterministic Pipeline Processing
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Solution Overview
Problem
Enterprises face challenges in efficiently allocating processing resources for data sets due to the non-deterministic nature of microprocessor processing, leading to over-allocation of resources, inefficient use of processing capacity, and difficulty in detecting processing errors in a timely manner.
Innovation Solution
A system that allocates field-programmable gate array (FPGA) resources by determining the minimum number of FPGAs needed based on data set size, available time, and operational clock speed, and categorizes data and FPGAs by processing requirements to optimize resource allocation and detect processing errors in real-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microprocessors are allocated to process data sets, then processing can be performed, but the non-deterministic nature makes it difficult to estimate processing time and ensures deadlines are met only by over-allocating resources
Solution Approach 1:
The patent replaces microprocessor-based software processing with FPGA-based hardware processing. FPGAs implement processing logic through configurable hardware circuits that execute operations in a deterministic manner, eliminating the non-deterministic behavior of microprocessors and enabling accurate processing time estimation without over-allocation
Solution Approach 2:
The patent changes the fundamental processing parameter from software-execution-time (non-deterministic) to hardware-circuit-propagation-time (deterministic). By configuring FPGAs with fixed logic circuits, the processing time becomes a measurable physical parameter based on signal propagation through hardware, allowing precise resource allocation
2Reliability
If timeout delays are used to detect processing errors, then error detection is possible, but the non-deterministic processing time requires unreasonable large timeout delays that are often ignored
Solution Approach 1:
The patent replaces the software-based timeout mechanism with a hardware-based timing mechanism. FPGA circuits can accurately measure and enforce processing time limits through deterministic hardware timers, eliminating the need for excessively large timeout delays that characterize microprocessor-based systems
3Reliability
If high processing capacity processing resources are allocated to data with low processing requirements, then resource availability is maintained, but processing efficiency decreases and data with higher processing requirements is queued
Solution Approach 1:
The patent applies local quality by matching specific FPGA resources to specific data processing requirements. The system configures and allocates FPGAs based on the actual processing needs of each data set, ensuring that processing capacity is neither excessive nor insufficient for any given task, thereby maximizing overall system productivity
Solution Approach 2:
The patent introduces dynamic resource allocation where FPGA configurations and allocations are adjusted based on real-time processing requirements. The system can reconfigure FPGAs and reallocate resources dynamically to match varying data processing demands, optimizing both resource availability and processing efficiency
Data Source
AI summary
A system for allocating field-programmable gate array (FPGA) resources comprises a plurality of FPGAs operable to implement one or more pipeline circuits, the plurality of FPGAs comprising FPGAs of different processing capacities, and one or more processors operable to access a set of data comprising a plurality of work items to be processed according to a pipeline circuit associated with each of the plurality of work items, determine processing requirements for each of the plurality of work items based at least in part on the pipeline circuit associated with each of the plurality of work items, sort the plurality of work items according to the determined processing requirements, and allocate each of the plurality of work items to one of the plurality of FPGAs, such that no FPGA is allocated a work item with processing requirements that exceed the processing capacity of the FPGA.