FPGA Routing Resource Testing via Subnetwork Segmentation

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Solution Overview

Problem

Testing routing resources in networks is challenging due to the need for complex IP blocks and external devices, which complicates the generation of test patterns and may not guarantee 100% fault coverage, especially when control and observation points are difficult to manage.

Innovation Solution

The system uses simpler structures, such as FPGA slices with Look Up Tables and flip-flops, to create pattern generator modules, and breaks the network into subnetworks to facilitate testing, eliminating the need for complex IP modules and minimizing routing resources required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex IP blocks are used to form source and load nodes for testing routing resources, then the test coverage can be improved, but the device complexity and difficulty of obtaining test modules increase

Engineering Contradiction:
Improvetest coverageVSAvoidmodule complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The complex IP block is segmented into two separate simple modules: a pattern generator module that generates test patterns and a checker module that verifies received patterns. This segmentation eliminates the need to obtain complex IP blocks while maintaining comprehensive test coverage of routing resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of using the actual complex IP block for testing, the invention creates simplified copies (pattern generator and checker modules) that replicate the essential testing functionality. These copies use simple logic elements like LUTs and flip-flops rather than complex IP circuitry.

Inventive Principle:
Principle #26Copying

2Reliability

If complex IP blocks are used for testing, then more routing resources can be tested, but the ease of operation and test procedure simplicity deteriorate

Engineering Contradiction:
Improverouting resource testing completenessVSAvoidtest procedure simplicity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The invention replaces complex IP blocks with simplified pattern generator and checker modules that are easier to program and operate. These modules use basic FPGA elements (LUTs, flip-flops) rather than complex proprietary IP, making the test procedure more accessible and simpler to implement.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The pattern generator module autonomously generates comprehensive test patterns without requiring external test equipment or complex setup. The checker module independently verifies the patterns received through the routing resources, eliminating the need for complex external testing infrastructure.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If challenging control and observation points are present in the network, then the network structure can be more functional, but the measurement precision and ability to generate test patterns deteriorate

Engineering Contradiction:
Improvenetwork functionalityVSAvoidfault detection capability
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The pattern generator and checker modules serve as intermediary elements that interface with the challenging control and observation points in the network. These simple modules can reliably generate and detect test patterns even when the network contains difficult-to-access control and observation points, ensuring comprehensive fault detection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7603599B1Method to test routed networks
Publication Date: 2009.10.13 XILINX INC
  • US7603599B1 patent drawing
  • US7603599B1 patent drawing
  • US7603599B1 patent drawing

AI summary

Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for testing a network path N to a load, subnetworks are created to perform testing. To provide the subnetworks, a source S′ is first provided close to node S that generates signal patterns to route through a path N′ to load L. When it is impractical to test a network path N from source to load L, a load L′ is further provided close to load L that receives the signal patterns from a routing path N″ provided from source S. The paths N′ and N″ overlap to cover all the routing resources of the path N.