FPGA RRAM Memory Cell Voltage Divider Interconnect
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face limitations in miniaturization, power consumption, and sensitivity due to the use of traditional SRAM memory cells, which are volatile, costly, and susceptible to radiation, while RRAM technology offers potential benefits like higher density and non-volatility but struggles with parasitic currents and resistance ratios.
Innovation Solution
The integration of RRAM memory cells with a voltage divider comprising programmable resistive elements and a pass gate transistor in FPGAs, allowing for high-speed programming and erasure, low power consumption, and improved resistance ratios, enabling smaller, faster, and more reliable devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional SRAM memory cells are used in FPGAs, then the device can be configured after manufacturing, but the component size is large, power consumption is high, and the device is susceptible to radiation
Solution Approach 1:
The patent changes the fundamental parameter of memory cell type from volatile SRAM to non-volatile RRAM, enabling configuration data to be retained without power. This transition reduces component size while maintaining reconfigurability, as RRAM cells require fewer transistors and can store configuration states permanently until reprogrammed
Solution Approach 2:
The patent segments the memory cell structure into distinct functional components: RRAM elements for configuration storage, voltage dividers for signal conditioning, and pass gate transistors for signal routing. This segmentation allows optimization of each component's size and function, contributing to overall miniaturization while preserving FPGA reconfigurability
2Adaptability or versatility
If traditional SRAM memory cells are used in FPGAs, then the device can be reconfigured, but power consumption is high
Solution Approach 1:
The patent changes the power consumption parameter by transitioning from volatile SRAM that requires continuous refresh power to non-volatile RRAM that retains configuration data without power. This eliminates standby power consumption while maintaining the ability to reconfigure the FPGA when needed
Solution Approach 2:
Instead of continuous power consumption for maintaining configuration state, the patent implements periodic reconfiguration actions where the FPGA is programmed only when configuration changes are needed. The RRAM retains the configuration state between programming events, converting continuous energy consumption into periodic action
3Ease of operation
If traditional SRAM memory cells are used in FPGAs, then the device can operate, but it is susceptible to radiation and noise
Solution Approach 1:
The patent changes the material parameter from SRAM transistor-based storage to RRAM resistive state storage. The resistive states in RRAM are inherently more resistant to radiation effects and noise, as they rely on physical filament structures rather than charge states that can be easily disrupted by environmental factors
Solution Approach 2:
The patent employs multiple RRAM elements in parallel within each configuration cell, creating redundancy. If one element is affected by radiation or noise, others can compensate, ensuring operational functionality. This approach uses simpler, more radiation-hardened RRAM elements rather than complex SRAM structures
4Area of stationary object
If basic RRAM cross-point cells are used, then component density increases, but parasitic currents cause slow read access
Solution Approach 1:
The patent introduces voltage divider circuits as intermediary elements between the RRAM configuration storage and the signal routing paths. These voltage dividers condition the signals from RRAM elements, amplifying or buffering them to overcome parasitic current effects and enable fast read access while maintaining the high density of the cross-point RRAM structure
Solution Approach 2:
The patent applies different functional qualities to different parts of the configuration cell: RRAM elements provide high-density non-volatile storage, voltage dividers provide signal conditioning and amplification, and pass gate transistors provide fast switching. This local differentiation of qualities allows each component to optimize its function, achieving both high density and fast read access
5Area of stationary object
If basic RRAM cross-point cells are used, then component density increases, but the resistance ratio between activated and deactivated states is insufficient
Solution Approach 1:
The patent uses composite RRAM structures with multiple resistive elements having different resistance characteristics. By combining elements with varying resistance ratios and characteristics, the overall configuration cell achieves a sufficiently high resistance ratio between activated and deactivated states while maintaining high component density
Solution Approach 2:
The voltage divider circuits act as intermediaries that enhance the effective resistance ratio by conditioning and amplifying the resistance differences from the RRAM elements. This allows the system to achieve reliable signal differentiation even when the raw RRAM resistance ratio is insufficient
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in FPGAs with enhanced component density, reduced power consumption, immunity to radiation, and faster power-up times, making them suitable for a broader range of applications with improved signal integrity and noise resistance.
Implementation Method 1
RRAM is a non-volatile memory technology that induces a filament (or many filaments) in a dielectric material. In a normal state, the dielectric has high resistance, and is non-conductive. However, application of a suitable voltage across the dielectric can induce a conduction path therein.
Implementation Method 2
A RRAM memory cell can include a voltage divider comprising multiple resistive elements arranged electrically in series across a common-collector voltage (VCC) and source-supply voltage (VSS) of the RRAM memory cell.
Data Source
AI summary
Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.