FPGA Rule Evaluation for Low-Latency Stream Processing

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Solution Overview

Problem

Conventional business rule processing systems face challenges with large and growing rule sets and data volumes, leading to high latency and potential bottlenecks in decision-making processes, especially when handling high-speed data streams.

Innovation Solution

The implementation of a hardware-accelerated rule condition check system using a coprocessor, such as a field programmable gate array (FPGA), which streams data and generates rule condition check results at bus bandwidth rates, reducing latency by performing operations like matching, filtering, and aggregation directly on incoming data streams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional business rule processing systems are used, then system simplicity is maintained, but processing latency increases and productivity decreases

Engineering Contradiction:
Improveprocessing latencyVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system segments rule processing into two distinct parts: a reconfigurable logic device (FPGA) that handles high-speed pattern matching and rule evaluation, and a conventional processor that manages rule set updates and complex control logic. This segmentation allows the time-critical matching operations to run in parallel hardware while keeping the overall system architecture manageable through clear separation of concerns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a reconfigurable logic device as an intermediary component between the conventional processor and the data stream. This intermediary handles the high-speed pattern matching and rule evaluation, acting as a buffer that prevents the conventional processor from becoming a bottleneck, thereby reducing overall processing latency without requiring complete system redesign.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If rule set size increases to handle more business requirements, then adaptability improves, but processing speed decreases

Engineering Contradiction:
Improverule set capacityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The reconfigurable logic device allows the rule processing architecture to dynamically adapt to different rule set sizes and complexities. The device can be reconfigured via firmware to accommodate varying rule sets without hardware changes, enabling the system to maintain high processing speeds while handling growing rule sets through dynamic reconfiguration rather than static design.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of rule processing from software-based sequential evaluation to hardware-based parallel evaluation. By altering the fundamental processing parameter from software instructions to hardware logic circuits, the system can evaluate multiple rules simultaneously, maintaining processing speed even as the number of rules increases to meet growing business requirements.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If data stream speed increases to meet real-time requirements, then responsiveness improves, but system bottleneck risk increases

Engineering Contradiction:
Improvedata processing throughputVSAvoidsystem bottleneck risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent replaces the mechanical/software-based rule processing system with a hardware-based reconfigurable logic device. This substitution transforms the processing mechanism from sequential software execution to parallel hardware evaluation, enabling the system to handle high-speed data streams without creating bottlenecks, as the hardware architecture is specifically designed to process multiple data elements simultaneously at line rate.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10965317B2Method and system for accelerated stream processing
Publication Date: 2021.03.30 CHARTER COMM OPERATING LLC
  • US10965317B2 patent drawing
  • US10965317B2 patent drawing
  • US10965317B2 patent drawing

AI summary

Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.