FPGA Runtime Signal Access via Configuration Memory Copy
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Solution Overview
Problem
Current FPGA-based real-time simulations face long development cycles due to the inability to freely access and modify model variables at runtime, requiring explicit routing and re-translation of signal values, which is time-consuming and resource-intensive.
Innovation Solution
A method that allows runtime access to FPGA signal values by reading status data from the FPGA's configuration memory without structural changes, enabling free access and manipulation of signal values like in software, without affecting the FPGA's operation or resource requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FPGA-based real-time simulation is used to meet tight time constraints and real-time requirements, then real-time performance is improved, but development cycles become significantly longer due to inability to access model variables at runtime
Solution Approach 1:
The patent creates a copy of the FPGA configuration memory contents to external memory, allowing runtime access to signal values without modifying the original FPGA structure. This copying mechanism enables experimentation tools to read and manipulate signal values while the FPGA continues to operate in real-time, thus resolving the contradiction between maintaining real-time performance and enabling flexible development iterations.
Solution Approach 2:
The patent introduces an intermediary layer (external memory and experimentation tool) between the FPGA and the user. This intermediary allows access to FPGA internal signals without requiring direct structural modifications to the FPGA hardware, enabling rapid prototyping and development while preserving the real-time execution capabilities of the FPGA.
2Ease of operation
If explicit routing of signal values through FPGA interfaces is implemented to enable access, then access capability is improved, but device complexity and development effort increase significantly
Solution Approach 1:
The patent extracts the signal value access function from the FPGA internal structure and relocates it to external memory. Instead of routing signals through complex FPGA interfaces, the configuration memory contents are copied externally, allowing simple read/write access without modifying the FPGA's internal signal routing architecture.
Solution Approach 2:
The patent makes the FPGA configuration memory serve multiple functions: it maintains its primary role in configuring the FPGA logic while also serving as a source for runtime signal value access. This multi-functionality eliminates the need for separate access pathways, reducing overall system complexity while maintaining ease of operation.
3Adaptability or versatility
If FPGA model re-translation is performed to access new signal values, then access flexibility is improved, but productivity decreases due to hours-long re-translation processes
Solution Approach 1:
The patent performs preliminary action by copying all configuration memory contents to external memory before runtime access is needed. This pre-copying enables rapid access to any signal value during development iterations without requiring time-consuming re-translation of the FPGA model, thus maintaining high adaptability while improving productivity.
Solution Approach 2:
The patent introduces dynamic access to signal values during runtime by reading from the copied configuration memory. This dynamic capability allows users to access and manipulate any signal value on-the-fly without static constraints of pre-defined FPGA interfaces, enabling flexible development iterations while maintaining high productivity through avoided re-translation cycles.
Data Source
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AI summary
An FPGA hardware configuration (24) with signal value is loaded onto FPGA (5). The FPGA hardware configuration on the FPGA is executed. The signal value for transmission to the FPGA is set. The writeback data is determined from the signal value, and is written as state data to configuration memory (8) of the FPGA. The state data is transmitted from the configuration memory to the functional level (6) of the FPGA. An independent claim is included for method for performing FPGA build.