FPGA Hardware Accelerator for SAT Solving via Parallel Inference
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Solution Overview
Problem
Conventional hardware solvers for the Boolean satisfiability problem (SAT) are slow and capacity-limited, making them obsolete and severely constrained.
Innovation Solution
A hardware accelerator using field-programmable gate arrays (FPGAs) for Boolean constraint propagation, with inference engines operating in parallel and utilizing Block RAM to store SAT instance information, allowing for efficient clause partitioning and implication inference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hardware solvers are used for SAT problems, then the system is simple to implement, but the solving speed is slow and capacity is limited
Solution Approach 1:
The patent divides the SAT solving system into multiple inference engines that operate in parallel, with each engine handling specific clauses. This segmentation enables the system to process multiple implications simultaneously, dramatically increasing solving speed while maintaining manageable complexity through modular architecture
Solution Approach 2:
The patent transitions from sequential software-based solving to parallel hardware-based solving by utilizing the spatial dimension of multiple inference engines operating concurrently. This dimensional shift from time-sequential to space-parallel processing is the key to achieving 3-40x speedup
2Productivity
If multiple inference engines operate in parallel, then SAT solving speed increases significantly, but memory management complexity increases
Solution Approach 1:
The patent introduces a clause partitioning technique as an intermediary layer that manages the distribution of clauses across multiple inference engines. This mediator handles the complex memory management and data distribution tasks, allowing parallel inference engines to operate efficiently without direct complex interactions
Solution Approach 2:
The patent creates a universal clause partitioning mechanism that can adaptively distribute clauses across different inference engines based on various criteria. This multi-functional partitioning approach handles both the organization of clause data and the balancing of workload across engines, simplifying individual engine operations
3Quantity of substance
If clause partitioning is optimized for minimum memory usage, then memory efficiency improves, but the partitioning problem becomes NP hard
Solution Approach 1:
The patent applies partial optimization by implementing a practical clause partitioning technique that achieves good memory efficiency without attempting to solve the complete NP-hard optimization problem. This approach accepts near-optimal solutions that are computationally feasible to obtain and update dynamically
Data Source
AI summary
A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.