FPGA Scan Chain Reduction for Faster JTAG Programming
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Solution Overview
Problem
Current programming systems for non-volatile computer data storage in integrated circuits, such as FPGAs, are inefficient due to lengthy scan chains defined by vendor-supplied BSDL models, leading to prolonged programming times for JTAG devices, especially as device complexity increases.
Innovation Solution
A scan chain modification system that reduces the number of registers in the FPGA scan chain to the minimum necessary for programming, using a chain modification module to generate a new data file that configures the device with a reduced scan chain, allowing for faster programming of non-volatile data storage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the default vendor-supplied BSDL model with full scan chain is used, then the device can be programmed according to industry standards, but the programming time becomes excessively long
Solution Approach 1:
The patent extracts and removes unnecessary registers from the scan chain, keeping only the minimum required for programming operations. The chain modification module analyzes the default BSDL model and eliminates redundant scan chain elements, thereby reducing programming time while maintaining essential functionality.
Solution Approach 2:
The patent changes the parameter of scan chain length by generating a modified BSDL model with a reduced number of registers. The chain modification module transforms the default model parameters to create an optimized scan chain configuration that is shorter and faster to program.
2Productivity
If the scan chain is reduced to minimum necessary registers, then programming time is significantly reduced, but the device may lose some standard compliance or functionality
Solution Approach 1:
The patent applies partial action by reducing the scan chain to only the necessary portion required for programming, rather than using the complete default scan chain. This partial configuration achieves the minimum viable scan chain length needed for JTAG compliance and programming operations.
Solution Approach 2:
The chain modification module performs preliminary analysis of the default BSDL model to identify and remove unnecessary registers before programming begins. This preliminary modification ensures that the reduced scan chain still maintains all essential functionality and standard compliance.
Data Source
AI summary
A non-volatile computer data storage programming system includes a scan chain modification configured to receive a default model defining a scan chain of an industry standardized device. A controller is in signal communication with the scan chain modification system, and is configured to program an industry standardized device. A non-volatile computer data storage device is configured to receive data from the industry standardized device. The scan chain modification system modifies the default model to generate a new model including a reduced scan chain, and the controller programs the industry standardized device based on the new model such that the industry standardized device is programmed with the reduced scan chain.