FPGA Security via Unique Authorization Codes
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Solution Overview
Problem
Existing Field Programmable Gate Arrays (FPGAs) face challenges in protecting configuration data from unauthorized cloning, reverse engineering, and overbuilding due to inefficiencies in key management, particularly in encrypting unique bitstream configurations for each device, which is impractical and insecure.
Innovation Solution
A cryptographic method using a unique-per-device secret key stored persistently, where the encryption key for the common configuration file is transported to each device via an ephemeral Authorization Code, allowing each device to decrypt and authenticate the bitstream independently, while the payload key is erased after use, enhancing security against cloning and reverse engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a unique key is used for each FPGA device to encrypt the configuration bitstream, then security against cloning and overbuilding is improved, but the complexity and cost of key management and bitstream generation increases significantly
Solution Approach 1:
The patent segments the key management process into two distinct phases: a setup phase where device-specific keys are generated and stored in non-volatile memory, and an operation phase where these stored keys are used to decrypt authorization codes. This segmentation allows unique per-device keys to be used without requiring complex real-time key generation and distribution mechanisms.
Solution Approach 2:
The patent applies preliminary action by pre-generating and storing unique per-device keys in non-volatile memory during the device manufacturing process. This preliminary key setup eliminates the need for complex key distribution during operation, as the keys are already in place and ready for use when the device needs to decrypt authorization codes.
2Ease of operation
If the same key is used for all FPGAs in a project to simplify key management, then ease of operation is improved, but security against overbuilding and unauthorized cloning deteriorates
Solution Approach 1:
The patent introduces asymmetry in the key management system by using different types of keys for different purposes: device-specific symmetric keys stored in non-volatile memory for decryption, and unique authorization codes for each device. This asymmetric approach allows the system to maintain ease of operation through standardized key storage while achieving secure per-device control through the asymmetric use of these keys.
3Reliability
If authorization codes are made unique per device to prevent overbuilding, then security is improved, but the amount of data that needs to be managed and transmitted increases
Solution Approach 1:
The patent extracts the essential security function from the authorization code by using a standardized code structure that can be decrypted by any device with the correct stored key. This extraction allows the system to maintain unique per-device authorization while reducing the data management burden by using a uniform code format across all devices.
Solution Approach 2:
The patent applies parameter changes by transforming the authorization mechanism from requiring large unique keys for each device to using smaller standardized authorization codes that are decrypted using the device's pre-stored key. This parameter transformation reduces the quantity of data that needs to be managed and transmitted while maintaining security.
Data Source
AI summary
A method for securely programming a population of authorized FPGAs includes defining the population of authorized FPGAs, generating an encrypted configuration bitstream for the population of authorized FPGAs, generating an individual Authorization Code for each FPGA in the population of authorized FPGAs, feeding the individual Authorization Codes into the FPGAs in the population of FPGAs, feeding the encrypted configuration bitstream into all of the FPGAs in the population of FPGAs, and in each FPGA using the Authorization Code to decrypt the encrypted configuration bitstream to program the FPGA.