FPGA Security IC Coupling via Encrypted Netlist Key
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Solution Overview
Problem
Field-Programmable Gate Arrays (FPGAs) lack the capability to securely store and manage cryptographic keys and establish secure communication sessions due to the absence of internal non-volatile storage and complex cryptographic algorithms, which violates Federal Information Processing Standards Publication 140 (FIPS 140) requirements, especially for bulk media decryption applications.
Innovation Solution
A shared secret key is incorporated into the FPGA net list, generated and encrypted with a password key, allowing secure authentication and communication between the FPGA and security IC, with the key stored in volatile memory to meet FIPS 140 zeroization requirements, using a coupling device that encrypts and decrypts the key for secure operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an FPGA is coupled to a security IC for bulk media decryption, then decryption throughput is improved, but security compliance with FIPS 140 deteriorates due to lack of secure key storage
Solution Approach 1:
A coupling device is introduced as an intermediary component between the FPGA and security IC. This coupling device includes a volatile memory interface that enables the FPGA to access encrypted shared secret keys stored in the security IC's non-volatile memory, thereby bridging the security requirements with the throughput capabilities.
Solution Approach 2:
The system is segmented into distinct functional components: the security IC handles key generation and secure storage, the coupling device manages key encryption/decryption and volatile memory operations, and the FPGA performs bulk decryption operations. This segmentation allows each component to fulfill its specific role while maintaining overall security compliance.
2Reliability
If cryptographic keys are stored in volatile memory in FPGA, then FIPS 140 zeroization requirements are met, but key persistence and availability deteriorate
Solution Approach 1:
The system performs preliminary actions by encrypting shared secret keys with a password key before storing them in the security IC's non-volatile memory. When the FPGA needs keys, it retrieves and decrypts them through the coupling device into volatile memory, ensuring they are available when needed but automatically zeroized when power is lost.
Solution Approach 2:
The system changes the state of cryptographic keys between encrypted form (stored in non-volatile memory in security IC) and decrypted form (temporarily held in volatile memory in FPGA). This parameter change allows keys to maintain persistence in encrypted form while enabling temporary availability in decrypted form for operations, with automatic zeroization when transitioning back to encrypted state or losing power.
3Ease of repair
If FPGAs use internal volatile memory for key storage, then key zeroization capability is improved, but security against unauthorized access deteriorates
Solution Approach 1:
The system uses a composite security architecture combining the security IC's secure non-volatile memory (with tamper-resistant properties) and the FPGA's volatile memory (with automatic zeroization). The coupling device bridges these two different memory types, allowing the system to leverage the security advantages of non-volatile storage while maintaining the automatic zeroization capability of volatile storage.
Solution Approach 2:
The coupling device acts as an intermediary that enforces security protocols between the FPGA and security IC. It controls access to encrypted shared secret keys, ensuring that keys are only made available to the FPGA through authenticated communication channels, thereby preventing unauthorized access while maintaining zeroization capability.
4Reliability
If a shared secret key is encrypted with a password key and incorporated into FPGA net list, then authentication security is improved, but system complexity deteriorates
Solution Approach 1:
The system merges the key generation, encryption, and authentication functions into the security IC, while the coupling device combines key management and volatile memory interface functions. This consolidation reduces overall system complexity by centralizing security-critical functions in dedicated hardware modules rather than distributing them across multiple components.
Data Source
AI summary
Disclosed is a mechanism for securely coupling a security IC and an FPGA. This mechanism creates a shared secret key; creates a password key; generates an encrypted shared secret key by encrypting the “shared secret key” with the password key; incorporates the “encrypted shared secret key” into an FPGA net list; programs the FPGA using the “FPGA net list”; transmits the “password key” from the security IC to the FPGA; allowing the FPGA to: obtain the “shared secret key” by decrypting the “encrypted shared secret key”; and store the “shared secret key” in at least one volatile memory location.