FPGA Segmentation for Legacy Bus Compatibility
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Solution Overview
Problem
Legacy systems face significant costs and development time when redesigned due to changes in available circuit components, such as Field Programmable Gate Arrays (FPGAs), which can render them inoperable or require costly updates to maintain communication between components.
Innovation Solution
The redesign of legacy systems involves partitioning the functionality of legacy FPGAs into first and second FPGAs, where the first FPGA is connected to a parallel bus and the second FPGA is connected via a high-speed serial interface, allowing for transparent communication without changing the legacy bus protocol, thereby enabling continued use of legacy bus protocols as an internal bus with minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If legacy FPGAs are replaced with newer FPGAs having fewer IO pins but high-speed serial interface functionality, then resource utilization is improved, but communication capability with parallel bus systems deteriorates
Solution Approach 1:
The legacy FPGA is segmented into two separate FPGAs: a first FPGA that interfaces with the parallel bus and a second FPGA that provides the additional functionality. This segmentation allows each FPGA to have optimized IO configurations - the first FPGA maintains parallel bus compatibility while the second FPGA can utilize high-speed serial interfaces, thus resolving the contradiction between reduced IO pin requirements and maintained communication capability.
Solution Approach 2:
The first FPGA acts as an intermediary between the parallel bus system and the second FPGA. It translates parallel bus transactions into high-speed serial interface communications, enabling the second FPGA (with fewer IO pins) to communicate effectively with the legacy parallel bus system without requiring the second FPGA to have direct parallel bus interface capability.
2Quantity of substance
If the second FPGA is not directly connected to the parallel bus, then resource constraints are satisfied, but communication transparency deteriorates
Solution Approach 1:
The first FPGA serves as a transparent intermediary that handles all protocol translation and address mapping. Legacy application software can access the second FPGA through the first FPGA using standard parallel bus transactions, making the indirect connection transparent to the software. The first FPGA intercepts transactions destined for the second FPGA, converts them to high-speed serial interface protocols, and manages the communication seamlessly in the background.
Solution Approach 2:
The first FPGA maintains a copy or mapping of the second FPGA's address space in the parallel bus address map. This allows the first FPGA to transparently redirect parallel bus transactions to the appropriate high-speed serial interface transactions, preserving the illusion of direct access for legacy software while enabling resource-efficient indirect connection.
3Adaptability or versatility
If legacy bus protocol is maintained without changes, then software compatibility is improved, but system performance deteriorates
Solution Approach 1:
The first FPGA acts as a protocol translation intermediary that maintains compatibility with the legacy parallel bus protocol while enabling high-speed serial communication. It translates slow parallel bus transactions into high-speed serial interface transactions, allowing legacy software to operate unchanged while achieving improved system performance through the use of faster high-speed serial interfaces for actual data transfer.
Data Source
AI summary
Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.