FPGA Safety Verification via Segmented Hardware Testing
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Solution Overview
Problem
Current methods for verifying safety apparatuses in critical infrastructure like nuclear power plants face challenges in ensuring high reliability due to software defects and the impracticality of exhaustive testing in digital systems, particularly with programmable logic devices like FPGAs, where defects from software tools and timing issues can go undetected.
Innovation Solution
A verification method that exhaustively tests all outputs of logic patterns on actual hardware, generates functional elements using a hardware description language, independently logic-synthesizes these elements, connects them, and verifies the operation of the programmable logic device to ensure normal functionality, including simulation-based verification for dynamic errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive testing is performed on all input and internal state patterns of an ASIC or FPGA, then complete verification of static function is achieved, but the verification process becomes impractical due to the huge number of patterns
Solution Approach 1:
The patent segments the verification process into two distinct phases: design-phase verification using simulation to check functional correctness, and manufacturing-phase verification using actual hardware testing to detect defects. This segmentation allows comprehensive verification without requiring exhaustive testing of all possible input patterns, as each phase focuses on specific aspects of verification that are feasible within practical constraints.
Solution Approach 2:
The patent performs preliminary verification during the design phase using simulation before the actual hardware manufacturing. By conducting simulation-based verification in advance, the patent can identify and correct functional defects early in the development process, reducing the burden on subsequent hardware testing and ensuring that only properly functioning designs proceed to manufacturing.
2Adaptability or versatility
If software is used for redundant system control, then system flexibility is improved, but the possibility of software defects impairing redundant system functionality increases
Solution Approach 1:
The patent employs identical hardware circuits for both the main system and redundant system, eliminating software complexity from the redundant path. By using the same hardware architecture for both systems, any defect in the redundant hardware would be immediately apparent during testing, ensuring that the redundant system can take over if the main system fails, thus maintaining reliability while preserving flexibility through hardware-level redundancy.
3Measurement precision
If digital processing is used instead of analog processing, then processing precision is improved, but the possibility of unexpected operations due to software and hardware defects increases
Solution Approach 1:
The patent incorporates self-verification mechanisms into the digital processing system where the redundant hardware circuit automatically monitors and compares the output of the main circuit. When a defect causes unexpected digital processing results, the redundant circuit detects the anomaly and triggers a safety response, enabling the system to self-diagnose and self-correct without external intervention, thus mitigating the harmful effects of digital defects.
Data Source
AI summary
A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.