FPGA SerDes Receiver Protocol Adaptation for UFS Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional automated test equipment (ATE) systems are limited in testing multiple devices under test (DUTs) due to processing load on the tester processor and bandwidth constraints, and they lack native support for Universal Flash Storage (UFS) protocols, restricting the ability to test UFS-compliant DUTs effectively.
Innovation Solution
The solution involves configuring off-the-shelf FPGAs with Serializer/Deserializer (SerDes) channels to communicate with UFS-compliant DUTs, allowing dynamic line rate changes for different speed modes and power saving states, thereby enabling concurrent testing of multiple UFS-compliant DUTs and reducing the processing load on the tester processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ATE systems use tester processor to generate commands and test patterns, then testing functionality is achieved, but processing load increases and limits the number of DUTs that can be tested concurrently
Solution Approach 1:
The system divides the testing functionality by separating command and test pattern generation from the tester processor and assigning it to individual FPGA devices. Each FPGA device now independently generates commands and test patterns for its associated DUT, eliminating the bottleneck where the tester processor had to generate all commands for multiple DUTs sequentially.
Solution Approach 2:
FPGA devices are configured to autonomously generate commands and test patterns without requiring continuous intervention from the tester processor. The FPGAs serve themselves by having built-in capabilities to create test sequences, reducing the processing burden on the central tester processor and enabling parallel operation across multiple DUTs.
2Adaptability or versatility
If conventional ATE systems use fixed protocol hardware adapters, then protocol-specific testing is enabled, but adaptability to different protocols (especially UFS) is limited
Solution Approach 1:
The FPGA devices provide universal protocol support by being reconfigurable through software configuration rather than requiring dedicated hardware for each protocol. A single FPGA device can be programmed to support multiple protocols including UFS, eliminating the need for separate protocol-specific hardware adapters and reducing system complexity.
Solution Approach 2:
The system changes the operational parameters of FPGA devices through software configuration to adapt to different protocols. By modifying the configuration bits and operational parameters of the FPGAs, the system can switch between different protocol modes (such as UFS high speed modes and power saving states) without physical hardware changes.
3Adaptability or versatility
If ATE systems support multiple speed modes for UFS protocol, then compatibility with UFS-compliant DUTs is improved, but system complexity increases
Solution Approach 1:
The system implements dynamic line rate adjustment in FPGA devices to support multiple UFS speed modes. The FPGAs can dynamically change their operating line rates based on the required speed mode (Gear 0-3), allowing the system to adapt to different performance requirements while maintaining a unified hardware platform.
Data Source
AI summary
A method for receiving data using an FPGA receiver circuit comprises receiving payload data from a DUT using a first rate of a plurality of line rates during a first burst, wherein the DUT is communicatively coupled to the FPGA receiver circuit. The method further comprises transitioning to a power saving state at an end of the first burst and receiving synchronization data from the DUT using a second rate of a plurality of line rates during a second burst. Further, the method comprises establishing synchronization with a clock data recovery (CDR) circuit of the FPGA receiver circuit at the second rate and receiving payload data from the DUT at the second rate.