FPGA SerDes Block With Phase-Shifted Oversampling for USB 2.0
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Solution Overview
Problem
Conventional FPGAs face challenges in handling high-speed USB 2.0 data rates due to limited device connectivity and the need for a CDR circuit, and typical serdes in FPGAs struggle to manage USB 2.0's high-speed mode without additional hardware.
Innovation Solution
A system with a configurable FPGA, a USB interface, and a bus that includes differential comparators to identify logic states, enabling high-speed data communication by oversampling data signals with phase-shifted clocks, and a serializer/deserializer block for efficient data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional FPGAs use typical serdes blocks, then device connectivity is maintained, but high-speed USB 2.0 data rate handling becomes difficult
Solution Approach 1:
The patent changes the operational parameters of the serdes block by integrating a CDR circuit that dynamically adjusts sampling timing and clock recovery parameters. This enables the serdes to operate at USB 2.0 high-speed rates (480 Mbps) by adapting the sampling rate and phase alignment parameters to match the incoming data stream characteristics, thereby resolving the contradiction between speed and adaptability.
Solution Approach 2:
The integrated CDR circuit within the serdes block provides multi-functionality by combining clock recovery, data sampling, and equalization capabilities in a single unified structure. This universal design enables the FPGA to handle multiple data rates (low-speed, full-speed, and high-speed USB modes) through a single serdes interface, eliminating the need for separate handling circuits and improving both speed and connectivity versatility.
2Speed
If conventional FPGAs deploy a CDR circuit, then high-speed USB 2.0 handling capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the CDR circuit functionality directly into the serdes block, combining clock recovery, data sampling, and signal equalization functions into a single integrated unit. This consolidation reduces device complexity by eliminating separate CDR and serdes circuits, while maintaining the ability to handle high-speed USB 2.0 data rates through the unified block's coordinated operation.
Solution Approach 2:
The integrated CDR circuit within the serdes block performs self-adjustment by automatically recovering the clock signal from the incoming data stream and dynamically adjusting sampling timing without external intervention. This self-service capability reduces the need for additional control logic and external circuitry, thereby reducing overall device complexity while enabling high-speed operation.
3Productivity
If FPGAs use GPIO for low-speed and full-speed USB, then resource consumption is reduced, but high-speed mode handling becomes difficult
Solution Approach 1:
The patent implements a dynamic serdes block with integrated CDR capability that can adapt its operational characteristics based on the detected data rate. The circuit dynamically adjusts sampling frequency, clock recovery parameters, and equalization settings to optimize performance for the current transmission speed, enabling efficient handling of high-speed USB 2.0 mode while maintaining resource efficiency through adaptive operation rather than dedicated high-speed hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates high-speed data transmission between a host and FPGA, supporting USB 2.0's 480 Mbps data rate with reduced clock drift and improved signal detection, enhancing flexibility and efficiency.
Implementation Method 1
a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel
Implementation Method 2
Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel
Implementation Method 3
a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift
Data Source
AI summary
A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.