Reconfigurable FPGA Interconnect via Serial Transceivers
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Solution Overview
Problem
Current methods for interconnecting multiple FPGA devices on a single circuit card are complex and costly due to the need for numerous parallel wiring configurations, which increase mechanical complexity and cost, and are not suitable for high-speed data transfer or signal processing.
Innovation Solution
The use of simplex and/or duplex serial I/O connections, such as multi-gigabit serial transceiver connections, to interconnect FPGA devices directly with minimal wiring, allowing for high bandwidth and low signal count connections, and the implementation of a reconfigurable communications infrastructure using packet-based switch fabrics and packet routers to facilitate communication between FPGA devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel wiring configurations are used to interconnect multiple FPGA devices, then data transfer bandwidth can be achieved, but mechanical complexity and cost increase significantly
Solution Approach 1:
The patent replaces mechanical parallel wiring systems with electrical serial communication systems. Instead of using multiple physical wires for parallel data transfer, the invention employs serial I/O connections that transmit data sequentially over fewer wires, thereby reducing mechanical complexity while maintaining data transfer capabilities through protocol-level parallelism
Solution Approach 2:
The patent segments the data transfer process into sequential serial transmissions rather than simultaneous parallel transmissions. By dividing data into individual bits or bytes transmitted over time on separate wires, the system achieves high bandwidth through time-division multiplexing while using fewer physical connection layers
2Speed
If parallel wiring configurations are used to interconnect multiple FPGA devices, then data transfer bandwidth can be achieved, but cost increases due to numerous wires and termination components
Solution Approach 1:
The patent substitutes expensive parallel wiring infrastructure with more economical serial communication infrastructure. By using standard serial I/O connections instead of multiple high-speed parallel wires with associated termination components, the system reduces material costs and assembly complexity while achieving comparable or superior data transfer performance
Solution Approach 2:
The patent employs universal serial communication interfaces that can handle multiple functions (data transfer, control signaling, configuration) over a single connection protocol, replacing the need for separate dedicated wires and termination components for each function, thereby reducing overall system cost
3Ease of manufacture
If JTAG serial interconnections are used for configuration purposes, then configuration can be achieved, but high-speed data transfer and signal processing functions are not suitable
Solution Approach 1:
The patent implements dynamic serial communication links that can be reconfigured between different operational modes. The same physical serial connection infrastructure used for configuration can be dynamically switched to high-speed data transfer mode, allowing the system to adapt its performance characteristics based on operational requirements without changing the physical wiring
Data Source
AI summary
Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.