FPGA Acceleration for Serverless Computing via Two-Stage Scheduling
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Solution Overview
Problem
Serverless computing faces challenges in accelerating data-intensive tasks due to the limitations of FPGA reprogrammability and dynamic workloads, requiring a scheduling mechanism that can intelligently switch between CPU and FPGA execution environments for optimal performance, while managing unpredictable data processing demands.
Innovation Solution
A two-stage scheduling scheme with initial placement and supplemental placement is implemented, allowing for fast and approximate scheduling decisions, and adjusting placements when further acceleration is needed, utilizing a shim layer, function registry, and data forwarding strategy to optimize task execution across multiple hosts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FPGA reprogramming is used to accelerate data-intensive tasks, then processing speed is improved, but system complexity increases due to dynamic workload management requirements
Solution Approach 1:
The patent introduces a task scheduler as an intermediary component that manages the complexity of FPGA reprogramming and workload distribution. The scheduler receives computing tasks, determines optimal placement between CPU and FPGA resources, and coordinates data forwarding between hosts and FPGAs, thereby shielding users from the underlying system complexity while enabling accelerated processing
2Ease of operation
If tasks are placed on a single host, then execution simplicity is maintained, but acceleration capability is limited when FPGA resources are unavailable locally
Solution Approach 1:
The patent segments the computing task into two independent placement decisions: initial placement of the main task to a host for execution simplicity, and supplemental placement of specific functions to remote FPGAs for acceleration. This segmentation allows the system to maintain simple task execution while selectively applying FPGA acceleration where available, resolving the contradiction between operational simplicity and acceleration capability
3Loss of time
If approximate scheduling is used for fast decisions, then response time is improved, but placement optimization is reduced
Solution Approach 1:
The patent implements preliminary approximate scheduling that makes fast initial placement decisions without exhaustive optimization. The task scheduler quickly assigns tasks to hosts and identifies potential FPGA acceleration opportunities, then performs supplemental placement optimization for specific functions. This two-stage approach reduces scheduling response time while maintaining adequate placement optimization through the supplemental phase
Data Source
AI summary
In one embodiment, a method for FPGA accelerated serverless computing comprises receiving, from a user, a definition of a serverless computing task comprising one or more functions to be executed. A task scheduler performs an initial placement of the serverless computing task to a first host determined to be a first optimal host for executing the serverless computing task. The task scheduler determines a supplemental placement of a first function to a second host determined to be a second optimal host for accelerating execution of the first function, wherein the first function is not able to accelerated by one or more FPGAs in the first host. The serverless computing task is executed on the first host and the second host according to the initial placement and the supplemental placement.