FPGA Shared Memory Interface Using Partial Reconfiguration
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Solution Overview
Problem
The overhead associated with data transfer between high-level modeling systems (HLMS) and hardware-based co-simulation platforms, particularly in simulations requiring large data transfers, limits performance in applications like real-time signal processing.
Innovation Solution
A shared memory interface utilizing partial reconfiguration capabilities of a Programmable Logic Device (PLD), such as a field programmable gate array (FPGA), allows for efficient data transfer between design blocks by implementing a shared memory on RAM resources and using partial reconfiguration to manage data access via a configuration bitstream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer between HLMS and hardware-based co-simulation platform is performed using traditional interfaces, then the system maintains simplicity in implementation, but the simulation performance deteriorates due to overhead in large data transfers
Solution Approach 1:
The patent merges the data transfer interface with the PLD configuration interface by using the configuration port for both purposes. The shared memory interface is implemented through the same configuration port that is used for PLD configuration, eliminating the need for separate dedicated data transfer interfaces and reducing overall system complexity while improving performance.
Solution Approach 2:
The configuration port of the PLD is made multi-functional by enabling it to serve both as a configuration interface for loading PLD bitstreams and as a data transfer interface for co-simulation. This universal interface approach allows high-speed data transfer without requiring additional dedicated hardware interfaces, thus improving simulation performance while maintaining interface simplicity.
2Productivity
If a shared memory interface is implemented using PLD configuration port for co-simulation, then data transfer overhead is reduced and simulation performance is improved, but the device complexity increases due to partial reconfiguration requirements
Solution Approach 1:
The patent implements dynamic reconfiguration of the PLD during runtime to enable shared memory access. The PLD is reconfigured from its original state to a state where shared memory interfaces are activated, allowing dynamic adaptation of the hardware structure to meet co-simulation data transfer requirements without permanent structural changes.
Solution Approach 2:
The patent performs preliminary configuration setup by establishing the shared memory interface through PLD reconfiguration before the actual co-simulation data transfer begins. The configuration bitstream is prepared and loaded in advance, setting up the shared memory structure and interfaces beforehand to enable efficient data transfer during the simulation runtime.
3Loss of time
If traditional data transfer methods are used between HLMS and hardware platform, then the implementation remains simple, but the simulation runtime increases due to transfer overhead
Solution Approach 1:
The patent introduces shared memory as an intermediary structure implemented in the PLD to facilitate data transfer between the HLMS and hardware-based co-simulation platform. This shared memory acts as a buffer and communication medium, enabling efficient data exchange without the overhead of traditional direct interfaces, thus reducing simulation runtime while managing interface complexity through a standardized memory interface.
Data Source
AI summary
Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.