FPGA Configuration Shift Register Reducing Chip Area
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Solution Overview
Problem
Field Programmable Gate Arrays (FPGAs) face challenges in efficient resource utilization and testability due to the significant space required by interconnection tracks and the need for additional features for testing functionality, which complicates manufacturing and increases resource consumption.
Innovation Solution
Implementing a Field Programmable Gate Array with a programming shift register configuration using flip flops instead of SRAM memory cells, allowing for programmable interconnection of lookup tables and enabling modes for testing and logic function implementation, which reduces resource usage and improves testability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM memory cells are used for configuration storage, then configuration data can be stored, but significant chip area is required for memory addressing and interconnection tracks
Solution Approach 1:
The patent combines configuration storage and test functionality into a single shift register structure. The same flip-flop elements that store configuration data are also used for testing through scan chain operation, eliminating the need for separate test structures and reducing overall chip area while improving testability.
Solution Approach 2:
The shift register serves multiple functions: it stores configuration data for the FPGA logic elements, enables testing through scan chain operation, and supports both programming and verification modes. This multi-functionality eliminates the need for dedicated test structures, reducing resource consumption.
2Reliability
If additional test structures are added to FPGA, then testability is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent merges test structures with the configuration storage structure. The shift register that holds configuration data is the same structure used for scanning during testing, eliminating the need for separate test structures and reducing overall device complexity.
Solution Approach 2:
The shift register structure performs both configuration storage and testing functions. By controlling the loading operation, the same structure serves as either a configuration memory or a scan chain for testing, reducing the need for additional dedicated test structures.
3Reliability
If scan chain testing is implemented, then testability is enhanced, but clock management complexity increases
Solution Approach 1:
The patent implements dynamic clock management where the clock signal to the shift register is controlled by an enable input. During normal operation, the shift register is clocked from the system clock; during testing, the same shift register can be clocked independently through the enable mechanism, allowing flexible test sequencing without additional clock infrastructure.
4Quantity of substance
If configuration values are stored in shift register, then chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a feedback mechanism where configuration values are loaded into the shift register and then read back for verification. The read-back values are compared with the original configuration data to detect any errors, ensuring manufacturing precision without requiring additional storage resources.
Data Source
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AI summary
Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.