FPGA Interconnect Testing with Shift Registers and Fewer I/O Pins
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Solution Overview
Problem
The testing of RAM-based FPGAs is time-consuming and costly due to the excessive number of I/O pads required for controlling and observing programmable logic blocks and interconnects, with existing methods unable to efficiently reduce the number of I/O pads needed for interconnect and logic block testing.
Innovation Solution
The implementation of vertical and horizontal shift registers placed in the center of the FPGA, perpendicular to each other, along with additional logic such as demultiplexers, allows for rapid interconnect testing by reducing the number of I/O pins required, enabling diagonal interconnect testing and parallel application and capture of test vectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional I/O pad testing method is used, then complete coverage of interconnect lines is achieved, but the number of I/O pads required becomes excessively large (160 pads for 80 lines)
Solution Approach 1:
Multiple interconnect lines are merged into single testable paths using snake-like routing patterns. Vertical lines are connected sequentially to form one continuous path, and horizontal lines are connected to form another continuous path, allowing multiple lines to be tested through fewer I/O pads.
Solution Approach 2:
Shift registers are introduced as intermediary components between the limited I/O pads and the extensive interconnect network. These registers enable serial access and control of multiple logic blocks through a small number of pads, acting as a mediator that expands the effective testing capability beyond the physical pad limit.
2Device complexity
If snake-like interconnect globalization is used to reduce I/O pads, then the number of pads is reduced from 160 to 4k, but the testing time becomes excessively large
Solution Approach 1:
The interconnect testing is segmented into multiple independent testable segments using the shift register architecture. Each logic block can be individually accessed and tested through the shift registers, allowing parallel test vector application to multiple segments simultaneously, thereby reducing total testing time despite using fewer pads.
Solution Approach 2:
The shift registers provide dynamic reconfigurable access to different interconnect segments. By dynamically shifting test vectors through the registers, the system can rapidly switch between different testing sequences and access different parts of the interconnect network, significantly accelerating the testing process compared to static snake-like routing.
3Ease of operation
If configuration inputs are used for testing, then test vectors can be applied, but the configuration process remains excessively time consuming due to serial bit entry
Solution Approach 1:
The slow serial configuration mechanism is replaced with a dedicated shift register-based test input mechanism. Instead of using the general-purpose serial configuration interface, the patent employs specialized shift registers that can rapidly load test vectors in parallel and apply them to the interconnect network, substituting the inefficient mechanical configuration process with a faster dedicated testing pathway.
Data Source
AI summary
A FPGA device that includes a plurality of programmable logic blocks connected to each other through interconnect resources, one or more sets of registers connected to the interconnect resources for configuring the programmable logic blocks. Additional logic is provided with the registers for selecting an interconnect/logic block testing mode thereby enabling a rapid interconnect/logic testing.