FPGA Signal Transmitter Buffering for Pixel Clock Adaptation
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Solution Overview
Problem
Existing signal transmitting/receiving devices require reconfiguration of the FPGA when the frequency of the pixel clock changes, leading to increased complexity and cost due to the need for external control and larger configuration ROM.
Innovation Solution
A signal transmitting/receiving device that uses a signal processing unit to convert parallel data from a first clock to a second clock with a constant frequency, eliminating the need for FPGA reconfiguration by using a first buffer memory and a transmitting unit formed of an FPGA, which converts parallel data into serial data and outputs it based on the second clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the FPGA is reconfigured when the pixel clock frequency changes, then the device can adapt to different video signal frequencies, but the device complexity increases due to the need for external control and configuration ROM
Solution Approach 1:
The patent applies the Dynamics principle by making the clock frequency adaptable through a buffer memory that can operate at different clock frequencies. The buffer memory dynamically adjusts between the first clock (pixel clock) for writing and the second clock (constant frequency) for reading, allowing the system to handle variable pixel clock frequencies without requiring FPGA reconfiguration. This dynamic frequency adaptation resolves the contradiction by providing versatility through clock frequency changes while maintaining fixed FPGA configuration.
2Adaptability or versatility
If the FPGA is reconfigured when the pixel clock frequency changes, then the device can adapt to different video signal frequencies, but the circuit size increases due to external control and configuration ROM
Solution Approach 1:
The patent applies the Taking out principle by extracting the frequency adaptation function from the FPGA and placing it in a buffer memory. Instead of reconfiguring the FPGA to handle different frequencies, the buffer memory is separated out to perform the frequency conversion between the first clock and second clock. This extraction reduces the FPGA's burden and eliminates the need for configuration ROM and external control circuits within the FPGA, thereby reducing the overall circuit size while maintaining adaptability.
3Adaptability or versatility
If the FPGA is reconfigured when the pixel clock frequency changes, then the device can adapt to different video signal frequencies, but the reconfiguration time is required which reduces system efficiency
Solution Approach 1:
The patent applies the Preliminary action principle by pre-establishing a buffer memory structure that is capable of operating at multiple clock frequencies without requiring reconfiguration. The buffer memory is designed in advance to handle both the first clock (variable pixel clock frequency) and the second clock (constant frequency), so when frequency changes are needed, the system simply switches clock frequencies rather than performing time-consuming FPGA reconfiguration. This preliminary design eliminates reconfiguration time while maintaining frequency adaptability.
Data Source
AI summary
The signal transmitting device of a signal transmitting/receiving device according to the present disclosure includes a signal processing unit that outputs a video signal as parallel data together with the first clock (the pixel clock); a first buffer memory to which the parallel data is written based on the first clock from the signal processing unit, and from which the written parallel data is read based on the second clock having a constant frequency equal to or higher than that of the first clock; and a transmitting unit. The transmitting unit receives the parallel data read from the first buffer memory and the second clock, converts the parallel data into serial data, and outputs the serial data to the signal line based on the second clock. The first buffer memory and the transmitting unit are formed of an FPGA (field-programmable gate array).