FPGA Signal Capture for Parallel In-Circuit Evaluation
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Solution Overview
Problem
Reconfigurable FPGA designs face challenges in debugging due to the complexity of modern designs, with traditional logic analysis methods being inefficient, and emulation being slow and expensive, leading to evaluation capturing over 50% of development time.
Innovation Solution
A method and device for evaluating FPGAs that involve configuring the FPGA to execute an evaluation program and an additional program in parallel, with a memory controller capturing signals from multiple points of interest and transferring them to a memory space or a host computer, allowing for flexible signal selection and storage based on triggers, errors, or user requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional logic analysis methods are used for debugging FPGA designs, then the debugging process can be performed with simple tools, but the evaluation process becomes extremely time-consuming and inefficient
Solution Approach 1:
The patent creates a virtual copy of the FPGA design logic within the FPGA itself to perform parallel evaluation. The evaluation logic replicates the functionality of the design under test, allowing simultaneous execution and monitoring without external emulation hardware, thus accelerating debugging while maintaining simplicity
Solution Approach 2:
The FPGA performs self-evaluation by containing both the design logic and evaluation logic within the same device. The evaluation program monitors the additional program's execution internally, eliminating the need for external emulation systems and reducing evaluation time significantly
2Measurement precision
If emulation is used for FPGA evaluation, then comprehensive signal capture and analysis capability is achieved, but the evaluation process becomes much slower and more expensive
Solution Approach 1:
The patent extracts only the essential evaluation functionality from external emulation systems and implements it directly within the FPGA. By taking out the core signal capture and monitoring capabilities and embedding them in the device, the system achieves comprehensive measurement precision while eliminating the speed limitations of external emulation
Solution Approach 2:
The patent merges the design logic and evaluation logic into a single integrated system within the FPGA. This combination allows the evaluation program to directly monitor signals from the additional program without external intervention, achieving both comprehensive signal capture and high evaluation speed simultaneously
3Loss of information
If comprehensive signal capture from multiple points of interest is implemented, then deep visibility into FPGA operation is achieved, but the complexity of the evaluation system increases
Solution Approach 1:
The patent implements a universal evaluation program that can monitor multiple points of interest simultaneously through a single integrated logic structure. The evaluation program is designed to handle diverse signal types and capture requirements uniformly, achieving deep visibility without proportionally increasing system complexity
Solution Approach 2:
The patent nests the evaluation logic within the same FPGA fabric as the design logic, with evaluation signals captured from internal nodes and processed through hierarchical monitoring structures. This nested arrangement allows comprehensive signal capture from multiple points while maintaining organized, manageable complexity through structured signal routing
Data Source
AI summary
A method for evaluation of a field programmable gate array (FPGA), the method includes: configuring the FPGA to execute, in parallel, an evaluation program and an additional program; wherein an execution of the additional program is being evaluated by the evaluation program; and executing, by the FPGA the evaluation program and the additional program; wherein the executing includes receiving, by a memory controller of the FPGA, captured signals from multiple points of interest of the FPGA; and transferring, by the memory controller of the FPGA, at least a portion of the captured signals to at least one memory space of a memory block via memory channels of the FPGA.