Reconfigurable FPGA Signal Capture for Error Localization
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Solution Overview
Problem
Existing logic analyzers for field programmable gate arrays (FPGAs) are limited in the number of signals they can extract and time width, making it difficult to acquire necessary signals for analysis, especially when abnormalities occur, and often fail to match the location of the acquisition with the actual error location or require insufficient time for analysis.
Innovation Solution
An information processing apparatus and integrated circuit that can reconfigure its logic circuit to acquire signal data from a dynamically set acquisition target position, using a narrowing-down unit to focus analysis on specific error locations and increase the amount of acquired waveform data by reconfiguring the FPGA device based on error classification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a logic analyzer is mounted on the FPGA to monitor internal state, then the internal operation can be analyzed, but the number of extractable signals and time width are limited, making it impossible to obtain necessary signals for analysis
Solution Approach 1:
The patent applies reconfigurability to the logic analyzer, allowing it to dynamically change its configuration based on error types. The system can reconfigure which signals to monitor and adjust time width parameters, transforming a static measurement device into a dynamic one that adapts to different analysis requirements, thereby overcoming the limitation of fixed signal extraction capabilities
Solution Approach 2:
The system changes operational parameters of the logic analyzer based on error classification. When an error occurs, the system identifies the error type and adjusts parameters such as the number of signals to monitor, the time width for waveform capture, and the specific acquisition locations, thereby optimizing the measurement capability for each specific error scenario
2Ease of operation
If signals are acquired from a fixed location in the FPGA circuit, then the acquisition process is simple, but the acquisition location may not match the actual error location, making analysis ineffective
Solution Approach 1:
The system implements a feedback mechanism where error information from the FPGA is analyzed to determine the error type and location, and this information is used to dynamically reconfigure the logic analyzer's signal acquisition parameters. This closed-loop approach ensures that the acquisition location is continuously optimized to match the actual error location, improving measurement precision while maintaining ease of operation through automated reconfiguration
3Speed
If the logic analyzer captures signals with limited time width, then the device operation is fast, but insufficient time width is obtained for analyzing abnormalities that require longer signal duration
Solution Approach 1:
The logic analyzer's time width parameter is made dynamic rather than fixed. Based on the classified error type and location, the system automatically adjusts the time width to the minimum necessary duration for effective analysis, avoiding both excessive capture times for simple errors and insufficient capture times for complex abnormalities, thereby optimizing the balance between analysis speed and signal duration
Data Source
AI summary
An information processing apparatus includes an integrated circuit that is capable of reconfiguring a logic circuit, executes data processing, and in a case where an error is generated in the data processing, acquires signal data from an acquisition target position set for a circuit portion that performs the data processing, and then outputs the signal data, a narrowing-down unit that narrows down an analysis target depending on the generated error, and a change unit that changes the acquisition target position depending on a result of a narrowing down by the narrowing-down unit after the signal data is output from the integrated circuit.