FPGA Interface Signal Remapping for Asynchronous Data Reliability
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Solution Overview
Problem
In nuclear power instrumentation and control systems, existing FPGA designs face issues with master clock signal transmission, two-way data transmission, signal transmission between asynchronous clock domains, and asynchronous reset signal transmission, leading to poor readability and debuggability, which hinders modular design and debugging.
Innovation Solution
The FPGA-based interface signal remapping method divides the internal programmable logic into an I/O module and a Core module, using the I/O module to process signal excursions, collisions, and errors, while the Core module handles logical processing, and introduces a master clock signal through a global clock pin, employing tri-state gate circuits and asynchronous FIFOs to manage data transmission and reset signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple signal transmission functions are integrated into a single FPGA chip, then device functionality is improved, but signal transmission reliability deteriorates due to signal excursion and collision
Solution Approach 1:
The patent divides the FPGA chip into two independent modules: an I/O module for handling external signal transmission and a Core module for logical processing. This segmentation isolates signal transmission functions from processing functions, preventing signal excursion and collision while maintaining versatile device functionality.
Solution Approach 2:
The patent introduces a signal remapping mechanism that acts as an intermediary between external signals and the FPGA Core module. This intermediary layer (I/O module) processes and cleans signals before they enter the Core module, ensuring signal reliability while preserving full device functionality.
2Device complexity
If signal transmission and processing functions are combined in one module, then device complexity is reduced, but readability and debuggability deteriorate
Solution Approach 1:
The patent segments the FPGA into an I/O module for signal handling and a Core module for processing. This clear separation improves readability and debuggability by isolating different functions, while the modular structure actually reduces overall system complexity through better organization.
Solution Approach 2:
The patent extracts signal transmission and I/O handling functions from the Core module into a separate I/O module. This extraction improves readability and debuggability by removing distracting signal-related code from the processing logic, while maintaining manageable device complexity through modular architecture.
3Speed
If asynchronous reset signal is transmitted directly to FPGA registers, then response speed is improved, but system stability deteriorates due to metastable state
Solution Approach 1:
The patent introduces a synchronizer circuit as an intermediary between the asynchronous reset signal and the FPGA registers. This synchronizer maintains fast reset response while converting the asynchronous signal into a synchronous one, preventing metastable states and ensuring system stability.
Solution Approach 2:
The patent performs preliminary synchronization of the reset signal before it reaches the registers. By preparing the reset signal in advance through the synchronizer circuit, the system achieves both fast response and stability, avoiding metastable states that would occur with direct asynchronous input.
4Device complexity
If two-way data signals share a single signal line, then device complexity is reduced, but data transmission reliability deteriorates due to collision
Solution Approach 1:
The patent introduces a tri-state gate as an intermediary in the shared signal line. This tri-state gate controls signal direction and prevents collision by blocking signals when not needed, allowing two-way data transmission over a single line with high reliability while maintaining low device complexity.
Data Source
AI summary
An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.