FPGA Signal Monitoring Circuit With Adjustable Sampling Window
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Solution Overview
Problem
Current methods for real-time debug and verification of programmable logic devices (PLDs) like FPGAs require external test equipment and software solutions, limiting the ability to monitor signals in an in-system operating environment.
Innovation Solution
An integrated circuit with programmable logic and interconnects, featuring an analog-to-digital converter, sampling bridge, and sample window circuitry that allows for in-system signal monitoring by generating reference signals and converting them into digital signals within the FPGA, enabling real-time diagnostics without external test benches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external test equipment and software solutions are used for real-time debug and verification, then signal monitoring capability is provided, but device complexity and ease of operation deteriorate due to required external connections and test benches
Solution Approach 1:
The patent combines the signal monitoring functionality with the FPGA device itself by integrating an analog-to-digital converter and sampling circuitry directly into the chip. This merging eliminates the need for external test equipment while maintaining real-time signal monitoring capability, thereby resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The FPGA performs self-diagnosis and self-monitoring through integrated ADC and sampling circuits that can capture and analyze its own internal signals without external assistance. This self-service capability removes the dependency on external test benches and software solutions, improving both reliability and ease of operation.
2Ease of operation
If external test benches are used for signal monitoring, then debug and verification are enabled, but ease of operation worsens due to required external connections
Solution Approach 1:
The patent merges the test bench functionality into the FPGA by integrating ADC and sampling circuitry directly on-chip. This eliminates external connections while preserving debug and verification capabilities, thereby improving ease of operation without increasing device complexity.
Solution Approach 2:
The integrated monitoring system enables the FPGA to perform self-diagnosis and self-verification without external test equipment. This self-service approach simplifies operation by removing the need for external connections and test benches while maintaining full debug capability.
3Reliability
If integrated ADC and sampling circuitry are added to FPGA, then in-system signal monitoring is enabled, but device complexity increases
Solution Approach 1:
The integrated ADC and sampling circuitry serve multiple functions: they monitor internal signals, enable real-time debugging, support verification activities, and facilitate in-system analysis. This multi-functionality justifies the added internal complexity by providing comprehensive monitoring capabilities without requiring separate external systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables real-time, in-system monitoring of signals within FPGAs, allowing for diagnostics and diagnostics to be performed while the device is operating, without the need for external test equipment, facilitating efficient debugging and verification.
Implementation Method 1
An analog-to-digital converter is disposed in an IC having programmable logic and programmable interconnect
Data Source
AI summary
In-system signal monitoring using an integrated circuit such as a programmable logic device is described. An analog-to-digital converter is disposed in the programmable logic device. A sampling bridge is coupled to provide an analog input to the analog-to-digital converter and to receive first signaling of a first frequency. A signal generator is configured to provide second signaling at a second frequency which is a fraction of the first frequency. Sample window circuitry is coupled to receive the second signaling and configured to provide third signaling to the sampling bridge at least partially responsive to the second signaling and at least partially responsive to an adjustable impedance setting of the sample window circuitry. The sample window circuitry is configured to provide an adjustable sample window within a pulse-width range.