Runtime FPGA Signal Modification via State Data Write-Back
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Solution Overview
Problem
Current FPGA-based real-time simulations face long development cycles due to the inability to freely access and modify model variables at runtime, requiring explicit modeling and re-translation of the entire model, which is resource-intensive and time-consuming, especially during calibration of control devices.
Innovation Solution
A method that allows signal values on an FPGA to be changed at runtime by writing state data into the functional level without structural changes, enabling direct access and modification of signal values like in CPU-based systems, without interrupting the FPGA operation, using a data processing device with a processor unit and an FPGA, and a computer program product to execute these steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA hardware configuration is recompiled to modify signal values, then signal value modification is achieved, but development cycle time increases significantly
Solution Approach 1:
The patent segments the FPGA configuration into two parts: static hardware structure (bitstream) and dynamic signal values (state data). By separating these concerns, signal values can be modified without recompiling the entire hardware configuration, thus reducing development cycle time while maintaining adaptability.
Solution Approach 2:
The patent performs preliminary action by translating Simulink model variables to FPGA state data during the build process. This pre-established mapping allows direct access and modification of signal values at runtime without requiring model retranslation, significantly reducing iterative development time.
2Adaptability or versatility
If explicit modeling and re-translation of entire model is performed, then signal value modification is enabled, but resource consumption increases
Solution Approach 1:
The patent extracts only the necessary state data corresponding to desired signal values from the FPGA configuration, rather than re-translating the entire model. This selective extraction approach enables signal value modification while minimizing computational resource consumption.
Solution Approach 2:
The patent creates a mapping between Simulink model variables and FPGA state data, allowing control software to access and modify signal values through this virtual copy rather than requiring actual model retranslation. This copying mechanism reduces resource consumption while maintaining full signal value accessibility.
3Adaptability or versatility
If FPGA operation is interrupted to modify signal values, then signal value changing is achieved, but real-time performance deteriorates
Solution Approach 1:
The patent implements dynamic modification of signal values during FPGA runtime by writing state data directly to the configured hardware. This dynamic approach allows signal value changes without interrupting FPGA operation, maintaining real-time performance while achieving full modifiability.
Data Source
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AI summary
The invention relates to a method for altering a signal value for an FPGA (5) at runtime, comprising the steps of loading an FPGA hardware configuration (24) with at least one signal value onto the FPGA (5), executing the FPGA hardware configuration (24) on the FPGA (5), setting the signal value for transmission to the FPGA (5), determining write‑back data from the signal value, writing the write‑back data as state data to a configuration memory (8) of the FPGA (5), and transmitting the state data from the configuration memory (8) to the functional level (6) of the FPGA (5). The invention furthermore relates to a method for performing an FPGA build on the basis of an FPGA model (20) in a hardware description language, comprising the steps of creating an FPGA hardware configuration (24) with a plurality of signal values, arranging signal values in adjacent regions of the FPGA hardware configuration (24), ascertaining memory locations (9) in a configuration memory (8) for state data for the plurality of signal values on the basis of the FPGA hardware configuration (24), creating a list containing signal values that can be accessed at runtime and the corresponding memory locations (9).