FPGA Simulation System for Early Design Flaw Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FPGA design processes lack effective tools to compare physical and logical designs, leading to delayed detection of faults and increased development costs due to the inability to identify deviations between behavioral and physical models during simulation.
Innovation Solution
A simulation system that configures a logic simulator to operate with an HDL model interfacing with an implemented FPGA, collecting input and output values, and comparing them to verify the FPGA's operation against the design model, thereby identifying faulty components and reducing the time to detect design faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a serial step-wise design process is used for FPGA development, then the design can be systematically implemented through RTL coding, logic simulation, synthesis, and place and route, but faults and deviations between behavioral and physical models cannot be detected early, leading to delayed fault detection and increased development costs
Solution Approach 1:
The patent applies preliminary action by performing physical model extraction and comparison with behavioral models during the synthesis stage, before place and route is completed. This allows faults to be detected early in the design process rather than waiting until hardware validation, thereby reducing fault detection time while maintaining systematic design implementation
Solution Approach 2:
The patent introduces an intermediary comparison mechanism that extracts physical models from the synthesis output and compares them against behavioral models. This intermediary comparison process enables early fault detection by identifying deviations between intended and actual design behavior before the design is finalized
2Productivity
If proprietary design tools are used for large FPGA devices, then the tools can handle the size and density of modern FPGAs, but the inability to compare physical and logical designs prevents early detection of tool-introduced flaws
Solution Approach 1:
The patent applies copying by creating a physical model copy from the synthesis output that can be compared against the behavioral model. This copied physical representation enables verification of the proprietary tool's work without requiring additional hardware validation, making flaw detection possible while maintaining full design implementation capability
Solution Approach 2:
The patent implements feedback by comparing the extracted physical model against the behavioral model and using this comparison to identify deviations. This feedback mechanism provides information about tool-introduced flaws, enabling detection of design issues that would otherwise remain hidden when using proprietary tools
3Reliability
If behavioral models are used for logic simulation, then the design behavior can be verified before implementation, but there is no mechanism to verify that the physical implementation matches the behavioral model
Solution Approach 1:
The patent introduces an intermediary physical model extraction process that bridges the gap between behavioral models and physical implementation. This extracted physical model serves as a mediator that can be compared against the behavioral model, preventing loss of information about implementation deviations while maintaining behavioral verification
Solution Approach 2:
The patent applies parameter changes by transforming the synthesis output into an extractable physical model format that can be directly compared with behavioral model parameters. This parameter transformation enables verification of whether the physical implementation matches the behavioral specification, recovering information that would otherwise be lost
Data Source
AI summary
A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and/or faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution.