FPGA Processing Circuit Soft Error Handling
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Solution Overview
Problem
In mission-critical systems that utilize field-programmable gate arrays (FPGAs), soft errors caused by radiation can lead to bit inversions in configuration memory, resulting in device malfunctions and unreliable outputs. Existing solutions require error correction and retry mechanisms, and the implementation of a spare processing circuit consumes valuable FPGA resources.
Innovation Solution
A data processing system is designed with a processor implemented by a programmable device, featuring multiple processing circuits that execute commands in parallel. An error detection unit identifies soft errors, and a processing circuit selection unit dynamically selects a different processing circuit to continue command execution, excluding the faulty one.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a spare processing circuit is prepared to provide resistance to soft errors, then system reliability is improved, but FPGA circuit resources are consumed
Solution Approach 1:
The processing circuit is divided into multiple independent processing units (first processing circuit, second processing circuit, etc.) that can operate in parallel. When a soft error occurs in one unit, the other units continue to process data, effectively segmenting the failure impact and eliminating the need for a complete spare system.
Solution Approach 2:
The system dynamically switches between processing circuits based on error detection. The circuit selection unit monitors for soft errors and switches to an alternative processing circuit only when needed, rather than having all circuits idle or requiring a permanent spare. This dynamic approach optimizes resource utilization while maintaining reliability.
2Reliability
If error correction and retry mechanisms are implemented, then soft error impact is reduced, but system operation time is increased
Solution Approach 1:
Multiple processing circuits are prepared in advance and configured to execute the same data processing commands in parallel. When a soft error is detected in one circuit, the system immediately switches to another pre-configured circuit without waiting for error correction or retry operations, thus minimizing time loss.
Solution Approach 2:
The circuit selection unit acts as an intermediary that monitors processing circuit status and redirects command execution to alternative circuits when soft errors are detected. This intermediary mechanism enables seamless fault tolerance without requiring time-consuming error correction or retry processes.
Data Source
AI summary
A data processing system includes: a processor implemented by a programmable device; and a processor processing unit connected to the processor. The processor includes a plurality of processing circuits configured to execute in parallel data processing commands provided from the processor processing unit, an error detection unit configured to detect a soft error occurring in a processing circuit that is executing the data processing command, and a processing circuit selection unit configured to select a processing circuit to execute the data processing command from a plurality of processing circuits. The processing circuit selection unit specifies a processing circuit in which the soft error occurs based on a soft error detection result of the error detection unit, and selects a processing circuit to execute the data processing command from the plurality of processing circuits, excluding the processing circuit in which the soft error occurs.