FPGA SPI Memory Access for Faster Configuration Updates

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Solution Overview

Problem

Conventional FPGA and PLD devices have limited capability to access and update configuration data efficiently, and JTAG operations are slow and cumbersome.

Innovation Solution

A PMA system with an FPGA, controller, and NVM is introduced, utilizing SPI ports for direct memory access, enabling flexible and efficient configuration data transfer through MSPI and SSPI ports.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If JTAG operation is used to access and update configuration data, then the FPGA can be programmed after fabrication, but the access speed is slow and the operation is cumbersome

Engineering Contradiction:

ImproveprogrammabilityVSAvoidconfiguration data access speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent introduces an intermediary SPI interface layer between the host controller and FPGA configuration memory. This SPI interface acts as a mediator that enables faster configuration data transfer compared to direct JTAG access, while maintaining the programmability feature of FPGAs

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical/JTAG-based configuration interface with an electronic SPI interface system. This substitution uses standard SPI communication protocols and timing signals instead of the slower JTAG boundary scan mechanism, thereby increasing configuration data access speed

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If dedicated custom integrated circuits or ASICs are used to meet demand for faster and flexible hardware, then processing capability is improved, but resource consumption increases and flexibility is lost

Engineering Contradiction:

Improveprocessing speedVSAvoidflexibility

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent makes the FPGA universally applicable by enabling it to access configuration data through multiple interfaces (both JTAG and SPI). This multi-functionality allows the same FPGA device to be used in different application scenarios requiring either slow but flexible JTAG programming or fast SPI configuration, eliminating the need for dedicated ASICs in each case

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If conventional FPGA approaches are used to maintain flexibility, then adaptability is preserved, but the capability to access and update configuration data efficiently is limited

Engineering Contradiction:

ImproveflexibilityVSAvoidconfiguration data update efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent makes the configuration interface dynamic by allowing the FPGA system to switch between JTAG and SPI interfaces based on operational needs. During initial programming, JTAG is used for its simplicity; during runtime updates or high-speed configuration, SPI is activated. This dynamic interface selection maintains flexibility while significantly improving configuration data update efficiency

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12547558B2Method and system for accessing a nonvolatile memory via SPI ports

Publication Date: 2026.02.10 GOWIN SEMICON CORP LTD

AI summary

A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.