FPGA SRAM Layout With RC-Balanced Paths for Pattern Alignment
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Solution Overview
Problem
Integrating SRAM-based FPGA devices with configuration devices and peripheral logic devices is challenging due to differences in design rules and technology, leading to issues with power, performance, and area (PPA), as well as MEOL pattern uniformity and BEOL alignment problems.
Innovation Solution
Designing and manufacturing SRAM-based FPGA and configuration devices according to logic rules and technology, using finfet and stacked nanosheet transistor technology, with EUV lithography for pattern uniformity, and implementing 6T SRAM circuits with RC-balanced conductive paths and aligned power/reference lines for improved integration and PPA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SRAM-based FPGA devices are integrated with configuration devices using different design rules and technology, then device functionality is enhanced, but manufacturing precision and pattern uniformity deteriorate due to alignment problems between FEOL/MEOL/BEOL layers
Solution Approach 1:
The patent applies homogeneity by designing both the SRAM-based FPGA device and the configuration device according to the same logic design rules and technology standards. This ensures that all components throughout the device, including different functional blocks and interconnect layers, follow uniform design criteria, which directly resolves the alignment and pattern uniformity issues that arise when integrating components with different design rules.
2Reliability
If additional components such as configuration device and non-volatile memory are added to SRAM-based FPGA devices, then data retention capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the SRAM-based FPGA device and the configuration device into a single integrated device structure. By combining these previously separate components into one unified device, the patent reduces overall system complexity while maintaining the data retention capabilities provided by the configuration device and non-volatile memory components.
Solution Approach 2:
The integrated device structure serves multiple functions: it provides FPGA logic functionality through the SRAM-based configurable logic, data retention through the configuration device, and persistent storage through the non-volatile memory. This multi-functional integration allows a single device to replace what would otherwise require multiple separate components, thereby reducing system complexity.
3Reliability
If 6T SRAM circuits are used with RC-balanced conductive paths, then power line robustness is improved, but manufacturing precision requirements increase due to alignment constraints
Solution Approach 1:
The patent applies homogeneity by ensuring that the conductive paths for RC-balanced 6T SRAM circuits are designed with consistent dimensions and characteristics throughout. By making all conductive paths uniform in their design parameters, the patent achieves power line robustness through proper RC balancing while avoiding the need for ultra-precise manufacturing, as uniform structures are more tolerant to manufacturing variations.
Data Source
AI summary
A semiconductor device includes a first transistor including a first drain/source terminal and a second transistor including a first gate terminal. A first conductive path is electrically connected between the first drain/source terminal and the first gate terminal. The first conductive path includes a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer, and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer.