FPGA and SSD Pairing via SMBus Interface

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Solution Overview

Problem

In densely populated server environments, the pairing of Field Programmable Gate Arrays (FPGAs) and Solid State Drives (SSDs) is not effectively established, leading to data corruption and incorrect results due to the lack of clear physical association, especially in virtualized environments where multiple devices appear as separate single-function devices, causing issues with peer-to-peer computing and requiring complex user knowledge to manage.

Innovation Solution

A new SSD device class is introduced with a private hardware interface like System Management Bus (SMBus) for FPGA and SSD communication, along with updates in firmware and software interfaces to query and advertise pairing attributes, enabling the SSD and FPGA to identify and pair with each other, and expose these details to the operating system and applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple FPGA/SSD pairs are densely populated in a server, then device density and performance are improved, but pairing identification becomes impossible and data corruption occurs

Engineering Contradiction:
Improvedevice densityVSAvoidpairing identification
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the identification problem by assigning unique identifiers to each device (FPGA and SSD) and creating distinct pairing records that link specific devices. This segmentation allows the system to track individual device pairings even when multiple pairs are densely populated, preventing identification conflicts and data corruption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary pairing identification mechanism that mediates between the FPGA and SSD devices. This intermediary system maintains pairing information and enables the host to correctly associate FPGAs with their paired SSDs, even in densely populated environments where direct device association is not visible.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If PCIe pass-through is enabled in virtualized environments, then device functionality is improved, but device pairing information is lost and multi-function devices appear as separate single-function devices

Engineering Contradiction:
Improvevirtualization supportVSAvoidpairing information
Core Design Contradiction:
Adaptability or versatilityVSLoss of information

Solution Approach 1:

The patent applies preliminary action by establishing and recording device pairing information before virtualization or PCIe pass-through is enabled. The pairing identification is set up in advance and preserved through the virtualization process, allowing the system to maintain correct device associations even when devices appear as separate single-function devices in the virtualized environment.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If separate physical functions are exposed for FPGA and SSD, then device functionality is improved, but pairing association becomes invisible and peer-to-peer computing fails

Engineering Contradiction:
Improvedevice functionalityVSAvoidpairing association
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The patent implements feedback by creating a pairing identification system that provides information about device associations back to the host and applications. This feedback mechanism allows the system to maintain awareness of FPGA-SSD pairings despite the devices appearing as separate physical functions, enabling peer-to-peer computing to function correctly.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10990554B2Mechanism to identify FPGA and SSD pairing in a multi-device environment
Publication Date: 2021.04.27 SAMSUNG ELECTRONICS CO LTD
  • US10990554B2 patent drawing
  • US10990554B2 patent drawing
  • US10990554B2 patent drawing

AI summary

A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.