FPGA State Machine Block for High-Level Synthesis
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Solution Overview
Problem
The slowdown in traditional semiconductor technology scaling has led to diminishing returns in computing performance and energy efficiency, while programming Field Programmable Gate Arrays (FPGAs) remains challenging due to their low-level design flow, making it difficult to efficiently utilize them for large-scale applications.
Innovation Solution
A novel mix-grained architecture for Finite State Machine (FSM) implementation that exploits characteristics of HLS-generated designs to reduce the area and critical path delay of FSMs, integrated into existing FPGA architectures, using a specialized hard block and state encoding technique to improve area efficiency without affecting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional semiconductor scaling is continued, then computing performance and energy efficiency should improve, but the rate of improvement is slowing down
Solution Approach 1:
The patent segments the computing system into heterogeneous components: general-purpose CPU cores for control and sequencing, and specialized accelerator units for specific computational tasks. This segmentation allows each component to be optimized independently, with accelerators performing computations in parallel to overcome the limitations of traditional sequential processing and restore performance growth without proportionally increasing energy consumption.
Solution Approach 2:
The patent changes the architectural parameters by introducing a hybrid architecture that combines von Neumann-style CPU cores with data-flow-style accelerators. This parameter change in system organization allows computations to be distributed across multiple specialized units operating simultaneously, thereby improving overall productivity and energy efficiency by reducing the energy cost per computation through parallelization.
2Adaptability or versatility
If FPGAs are used for large-scale applications, then flexibility and reconfigurability are improved, but programming difficulty and design complexity increase
Solution Approach 1:
The patent introduces an intermediary layer of abstraction between the high-level C/C++ code and the low-level FPGA hardware implementation. The HLS compiler acts as a mediator that automatically translates software-like code into hardware descriptions, managing the complexity of resource allocation, timing constraints, and circuit optimization. This intermediary enables users to program FPGAs using familiar software languages while the toolchain handles the intricate hardware design details.
Solution Approach 2:
The patent replaces the manual, mechanical process of hardware design (writing Verilog/VHDL, manually placing and routing components) with an automated software-based system. The HLS toolchain automatically synthesizes high-level code into optimized hardware circuits, eliminating the need for designers to manually manage the complex details of FPGA configuration and circuit design, thereby reducing design complexity while maintaining reconfigurability.
3Productivity
If hard blocks are added to FPGA architecture, then performance and energy efficiency improve, but area overhead and resource usage increase
Solution Approach 1:
The patent implements a dynamic resource allocation mechanism where hard blocks are not statically assigned but are dynamically instantiated and configured based on the specific computational requirements of the loaded application. The FPGA architecture can adaptively activate only the necessary accelerator units for each task, allowing hard blocks to be shared across multiple applications and reducing the effective area overhead by avoiding dedicated hardware for every possible function.
Solution Approach 2:
The patent designs hard blocks with universal functionality that can perform multiple types of computations through reconfiguration. Instead of having separate dedicated hardware for each operation type, the accelerators can be dynamically programmed to handle different computational patterns (e.g., matrix operations, signal processing, arithmetic calculations), thereby reducing the total area required by allowing one hard block to serve multiple purposes across different applications.
Data Source
AI summary
An architecture for a Field Programmable Gate Array (FPGA) that better supports the designs of finite state machines (FSMs) generated by High-Level Synthesis (HLS) tools. The architecture is based on categorizing states of a FSM into branch free path states and independent states. A memory unit stores next state information for independent states and an accumulator unit computes next state information for branch free path states. A control unit selects the next state based on either the memory unit or the accumulator unit. An input sequence encoder encodes external inputs and current state values into encoded sequence signals that are input to the memory unit. Also disclosed is a state assignment algorithm that assigns state values to states of the FSM by first identifying branch free paths that terminate on the same state and then eliminating overlap between paths. States along the same branch free path are assigned sequential values.